Synthesis of arrays and records
AssigneeInternational Business Machines Corporation
InventorsStephen Barnfield, Reinaldo A. Bergamaschi, Pradip K. Jha, Rudra Mukherjee, John D. Weaver
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Abstract
A method for synthesizing aggregate data types, in accordance with the present invention, includes representing aggregate data types in a control data flow graph, by representing aggregate objects as operand nodes, and operations on the aggregate objects as operation nodes. One-dimensional bit vectors are formed for the operand nodes, by recursively traversing through fields of the aggregate data type associated with the aggregate objects. Read and write operation nodes are formed in the control data flow graph for representing language constructs for accessing the aggregate objects. The control data flow graph is mapped onto hardware.
Claims21
A method for synthesizing aggregate data types comprising the steps of:
- representing aggregate data types in a control data flow graph, by representing aggregate objects as operand nodes, and operations on the aggregate objects as operation nodes;
- forming one-dimensional bit vectors for the operand nodes, by recursively traversing through fields of the aggregate data type associated with the aggregate objects;
- forming read and write operation nodes in the control data flow graph for representing language constructs for accessing the aggregate objects;
- and
- mapping the control data flow graph onto hardware.
A method for synthesizing aggregate data types, including multi-dimensional arrays, records and nested data structures, comprising the steps of:
- representing aggregate data types in a control data flow graph, by representing aggregate objects as operand nodes, and operations on the aggregate objects as operation nodes;
- forming one-dimensional bit vectors for the operand nodes, by recursively traversing through fields of the aggregate data type associated with the aggregate objects;
- forming read and write operation nodes in the control data flow graph for representing language constructs for accessing the aggregate objects;
- mapping the control data flow graph onto hardware by representing the operand nodes as one of at least one storage element and a net, based on register inference rules of very high speed integration circuit hardware description language (VHDL) synthesis;
- and
- mapping the control data flow graph onto hardware by mapping the operation nodes of the control data flow graph for a plurality of addressing methods.
Dependencies are inferred from the claim text.