Method and system for creating and validating low level description of electronic design

A system for providing an integrated system environment within an electronic computer aided design system for creating a design of an integrated circuit chip, comprising:

• a memory;
• a synthesis memory compiler for synthesizing said memory into a memory block comprising a netlist of primitive transistors;
• a translator, which translates the memory block into data which may be read by a design compiler;
• a modeler, which models mega cells and macro cells;
• and
• an optimizer.

A system for providing an integrated system environment within an electronic computer aided design system for creating a design of an integrated circuit chip, comprising:

• a plurality of mega-cells and mega-functions;
• a modeler, which models mega-cells and macro-cells;
• a netlist back plane;
• and
• an optimizer.

A system for providing an integrated system environment within an electronic computer aided design system for creating a design of an integrated circuit chip, comprising:

• a design compiler which provides an environment for synthesis and constraint driven optimization and synthesizes random logic;
• a netlist back plane;
• and
• an optimizer.

A method for designing an integrated circuit chip, comprising the steps of:

• formulating a behavioral description of the design in a high-level language;
• partitioning the behavioral description into architectural blocks;
• synthesizing both structured and unstructured logic;
• creating a netlist;
• compiling and simulating the netlist;
• and
• providing a structural description of the design to a target compiler.

A method of designing a circuit using an electronic computer aided design system, comprising the steps of:

• formulating a description of the desired behavior of the circuit;
• reformulating the circuit design description as a register-level transfer description of the circuit;
• simulating the register transfer level description, wherein said simulating step equates to the behavioral description;
• and
• minimizing simulated logic associated with the design.

A method of partitioning a design of an integrated circuit chip by imposing predetermined constraints, comprising the steps of:

• initially scheduling intrinsic delays among functional units of the design;
• binding the design by assigning registers and multiplexers to the functional units;
• estimating timing for the bound design;
• determining whether the design meets timing constraints;
• establishing priority factors for said predetermined constraints;
• estimating values for said predetermined constraints;
• evaluating whether said predetermined constraints satisfy a predetermined criteria;
• and
• calculating a cost function and repeating said value estimation and evaluation steps until said predetermined constraints satisfy a predetermined criteria.

A method for creating and validating a description of an electronic design, comprising:

• specifying a desired behavior for the electronic design;
• partitioning the electronic design into a number of blocks;
• utilizing logic synthesis programs to provide a low-level description of the electronic design;
• and
• estimating timing parameters for physical implementation of the electronic design.

A method for creating a structural description of a circuit or device from a high-level design within a mutli-windowing graphical user interface (GUI) environment, comprising the steps of:

• specifying a description of the high-level design in a behavior-oriented language;
• partitioning the high-level design into a plurality of clusters;
• performing a detailed physical floorplan of the design, wherein said physical floorplan is performed utilizing:
• analysis tools to evaluate predetermined performance criteria;
• and
• planning tools;
• and
• iteratively evaluating and correcting the detailed physical floorplan based on analysis and physical design evaluation.

A system for creating a structural description of a circuit or device on an ECAD device, comprising;

• a device for creating a behavior description of said circuit or device:
• a logic synthesis tool for synthesizing circuit design on a structural level from said behavioral description;
• and
• a floorplanning tool which feeds design information back to said logic synthesis tool to analyze and correct design deficiencies.