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AssigneesPrinceton University, NEC USA, Inc.
InventorsZhen Luo, Margaret Martonosi, Pranav Ashar
Estimating the term…
The method and apparatus for performing design rule checking on Manhattan structures in VLSI circuit layouts. The method and apparatus provides an edge-endpoint-based technique for checking the geometry and spacing of the VLSI circuit layout. The edge-endpoint-based technique uses a scanline algorithm that detects errors between adjacent structures that do not simultaneously intersect the scanline. The method also provides efficient error compilation. The apparatus allows for the design rules to be changed as the VLSI circuit layout evolves. The apparatus can process the VLSI circuit layout with a single processor, and the apparatus provides for multiple processors to process slices of the VLSI circuit layout, thereby enhancing the speed of the design rule checking over traditional software-only techniques.
The method for analysis of an integrated circuit mask layout against predetermined design rules using a scanline, comprising:
A computer system adapted for analysis of an integrated circuit mask layout against predetermined design rules using a scanline, comprising:
A computer program product for enabling a computer to perform analysis of an integrated circuit mask layout against predetermined design rules using a scanline, comprising:
An apparatus for analysis of an integrated circuit mask layout against predetermined design rules using a scanline, including:
An apparatus for analysis of an integrated circuit mask layout against predetermined design rules using a scanline, including:
Dependencies are inferred from the claim text.