Checksum generator with minimum overflow
AssigneeNovell, Inc.
InventorDana M. Henriksen
Life of this patent
Estimating the term…
Abstract
A checksum generator includes at least one adding circuit for processing a segment of a given message. Associated with the adding circuit is a register for temporarily holding the partial sum that is being calculated by the adding circuit. The register is configured to hold a partial sum that is larger than the message segments being added by the adding circuit. The partial sums can thus expand into the register, eliminating the creation of a carry bit that must be added back in during each add cycle. After the last message segment has been processed, the adding circuit preferably adds the high order portion of the register to the low order portion and adds back any carry bit generated thereby to produce a checksum value that may be loaded into the given message.
Claims20
A checksum generator for calculating a checksum value for a given message, the checksum generator comprising:
- at least one adder having first and second inputs, a sum output and a carry-bit return, the first input configured to receive a plurality of message segments, each message segment being n-bits in length;
- and
- at least one register coupled to the sum output to temporarily store a partial sum from the at least one adder, and to the second input to return its contents to the at least one adder, the register configured so as to be greater in size than the n-bit message segments received by the adder.
A checksum generator for calculating a checksum value for a given message, the checksum generator comprising:
- two or more adders each having first and second inputs and a sum output, at least one adder having a carry-bit return, the first input of each adder configured to receive a plurality of message segments, each being n-bits in length;
- and
- at least one register apportioned into two or more sections each coupled to the sum output of a respective adder to temporarily store a partial sum from the respective adder, each register section coupled to the second input of its respective adder to return its contents to the respective adder, each register section configured to be greater in size than the n-bit message segments received by the two or more adders.
A method for generating a checksum value for a given message split into one or more message streams, each message stream corresponding to a plurality of message segments each having a length of n-bits, the method comprising the steps of:
- configuring at least one data register into one or more sections for temporarily storing a partial sum, each register section having a size that is greater than n-bits;
- associating each of the one or more message streams with a selected register section;
- summing each message segment from the respective message streams with its associated register section to create a partial sum;
- placing the partial sums for each message stream in its associated register section such that the summing step is free from creating carry bits due to the one or more register sections being greater than n-bits in size;
- in response to summing last message segments in each message stream, adding the one or more register sections to create a first intermediate sum;
- placing the first intermediate sum in a first register section;
- apportioning the first register section into first and second register portions;
- adding the first and second register portions to create a second intermediate sum and a first carry value;
- and
- adding the second intermediate sum and the first carry value to obtain the checksum value.
Dependencies are inferred from the claim text.