Memory test device and method capable of achieving fast memory test without increasing chip pin number

Abstract

A memory test device that issues a test pattern read request to a memory, captures test pattern signals placed by the memory on a data input/output bus in response to the test pattern read request, and compares the test pattern signals with their expected values. This can solve a problem involved in a conventional memory test device in that because the pin width of data pins is narrower than the bus width of the data input/output bus that connects a memory and a data bus controller, even if the memory reads test pattern signals in accordance with the width of the data input/output bus, the test pattern signals cannot be sent to the tester without being divided, and hence the tester cannot achieve the quick test of the memory.

Dependencies are inferred from the claim text.