On-clip testing circuit and method for improving testing of integrated circuits

An integrated circuit comprising:

• a function circuit;
• an expect data register;
• a comparison circuit having first inputs coupled to the outputs of the function circuit and second inputs coupled to outputs of the expect data register;
• and
• a fail data register having an input coupled to an output of the comparison circuit, wherein the integrated circuit receives an expect data signal generated by a source other than the internal test circuit itself.

A computer system comprising:

• a data and address bus;
• a central processing unit coupled to the data and address bus;
• an input device coupled to data and address bus;
• a display coupled to the data and address bus;
• and
• a memory coupled to the central processing unit, the memory including a ROM storing instructions providing an operating system for the central processing unit and including a read-write memory providing temporary storage of data, the read-write memory including memory integrated circuits each comprising:
• a memory array;
• and
• an internal test circuit that receives an expect data signal generated by a source other than the internal test circuit itself, the internal test circuit comprising:
• an expect data register;
• a comparison circuit including first inputs coupled to outputs of the expect data register and second inputs coupled to the memory array;
• and
• a fail data register having an input coupled to an output of the comparison circuit, the fail data register storing information describing failed cells in the memory array.

An integrated circuit including an on-chip test circuit comprising:

• an expect data buffer having an input bus coupled to a source of expect data and having an output bus;
• a function circuit having inputs coupled to a source of background data;
• a data compare circuit having a first set of inputs coupled to outputs of the function circuit and a second set of inputs coupled to the output bus of the expect data buffer;
• and
• a fail data register having an input coupled to an output of the data compare circuit, wherein the source of expect data is a source other than the on-chip test circuit itself.

A method for speed grading an integrated circuit having an on-chip test circuit comprising:

• testing a function circuit in the integrated circuit at a first clock frequency using expect data provided by a source other than the on-chip test circuit to provide a first set of failure data;
• storing the first set of failure data in a fail data register in the integrated circuit;
• testing the function circuit at a second clock frequency using expect data generated by a source other than the on-chip test circuit to provide a second set of failure data;
• storing the second set of failure data in the fail data register;
• and
• downloading the first and second sets of failure data to an integrated circuit tester.

In an integrated circuit including a function circuit, a method of testing the integrated circuit comprising:

• resetting a fail data register in an on-chip test circuit in the integrated circuit;
• setting the on-chip test circuit to a testing mode;
• coupling background data to the function circuit;
• coupling expect data generated by a source other than the on-chip test circuit to the on-chip test circuit;
• extracting read data from the function circuit in response to the background data;
• comparing, by the internal test circuit, the read data to the corresponding expect data to determine when the function circuit fails;
• and
• storing failure data describing the failure of the function circuit in the fail data register when the function circuit fails.

A method for testing a plurality of integrated circuits comprising:

• coupling a common data bus to an I/O port of each integrated circuit;
• coupling a dedicated control line to each of the integrated circuits;
• supplying test data to the common data bus;
• determining, within each integrated circuit, when a failure occurs in a function circuit in the integrated circuit;
• and
• storing data in a counter describing the failure in the integrated circuit that had the failure occur when a failure is determined to have occurred.

A method for speed grading a plurality of integrated circuits comprising:

• coupling a common data bus to an I/O port of each integrated circuit;
• coupling a separate dedicated control line to each of the integrated circuits;
• supplying a first clock signal having a first frequency to each of the integrated circuits;
• supplying first test data to the common data bus;
• determining, within each integrated circuit, when a failure occurs in a function circuit in the integrated circuit;
• storing, in a counter in the integrated circuit that had the failure, first failure data describing the failure when a failure has occurred;
• supplying a second clock signal having a second clock frequency to each of the integrated circuits;
• supplying second test data to the common data bus;
• determining, within each integrated circuit, when a failure occurs in the function circuit;
• and
• storing, in the counter in the integrated circuit that had the failure, second failure data describing the failure when a failure has occurred.

A memory integrated circuit, comprising:

• a memory array;
• and
• an internal test circuit that receives an expect data signal generated by a source other than the internal test circuit itself, the internal test circuit comprising:
• a comparison circuit having a first input coupled to an output of the memory array and a second input that receives the expect data signal, the comparison circuit being operative to generate an output indicative of a comparison between signals applied to the first and second inputs;
• and
• a fail data register having an input coupled to receive the output of the comparison circuit, the fail data register storing data corresponding to the output of the comparison circuit.

An integrated circuit, comprising:

• a function circuit;
• a comparison circuit having a first input coupled to an output of the function circuit and a second input that receives an expect data signal generated by a source other than the integrated circuit itself;
• and
• a fail data register having an input coupled to an output of the comparison circuit.