Asynchronous switching circuit for multiple indeterminate bursting clocks

A clock-switching circuit that provides a single unclipped and glitch-free clock signal at its output from among multiple asynchronously-enabled clock input signals, said clock-switching circuit comprising:

• a plurality of asynchronously-enabled clock circuits;
• a plurality of blocking circuits, each of said plurality of blocking circuits having a disable lead, an enable lead, and an output lead, said enable lead providing an asynchronous signal to enable one of said plurality of asynchronously-enabled clock circuits respectively coupled to one of said plurality of blocking circuits, said output lead coupled to said disable lead of balance of said plurality of blocking circuits, said disable lead coupled to said output lead of balance of said plurality of blocking circuits, said disable lead disabling all of said plurality of asynchronously-enabled clock circuits except the one to which its input is coupled;
• a synchronizing clock, said synchronizing clock coupled to each of said plurality of blocking circuits;
• and
• a output logic gate, said output logic gate coupled to each of said plurality of asynchronously-enabled clock circuits, said output logic gate providing said unclipped and glitch-free output signal from a clock-switching circuit.

A method of switching between multiple clock input signals to provide a single unclipped and glitch-free output clock signal, said method comprising the steps of:

• a) receiving a plurality of clock signals at a clock-switching circuit;
• b) receiving a plurality of input signals, each of said plurality of input signals provided to enable and disable its respective one of said plurality of clock signals, each of said plurality of input signals having an enabling and a disabling logic level;
• c) switching an output signal of said clock-switching circuit from a first of said plurality of clock signals to a second of said plurality of clock signals only at time periods when said first and said second of said plurality of clock signals have a low-logic level;
• d) enabling one of said plurality of clock signals to be said output signal of said clock-switching circuit without clipping when its respective one of said plurality of input signals receives an enabling logic level and when a blocking signal has not been generated by any of said plurality of clock signals other than said enabled one of said plurality of clock signals;
• and
• e) generating a blocking signal to protect from potential conflict said one of said plurality of clock signals that is enabled as said output signal of said clock-switching circuit.