US 6,324,643 B1 · Branch prediction and target instruction control for processor

Abstract

A two level branch prediction system and method is disclosed for controlling instruction flow in a pipelined processor. A first prediction indicator associated with a branch instruction specifies whether a particular branch condition is likely to be satisfied. A second prediction indicator associated with a branch control instruction specifies whether a particular branch target instruction is likely to be needed by one or more of the branch instructions. The first prediction indicator is used to load branch target instructions as they are needed in response to decoding a branch instruction, while the second prediction indicator is used by prefetching logic within the processor to determine whether a particular branch target instruction should be speculatively loaded even before the associated branch instruction is executed. The first and second prediction indicators can be set in advance as bit fields in the branch and branch control instructions respectively so that the processor microarchitecture behavior can be set up and controlled in software to reduce branch latencies for a particular program. The second prediction indicators can be ranked as well so that the prefetching logic can prioritize speculative loadings in accordance with a desired strategy.

Claims21

Dependent claims

A method of controlling execution of branch instructions in a processor comprising the steps of:

providing a plurality of first indicators for each of a plurality of branch instructions, such that each of said plurality of branch instructions includes an associated first indicator predicting an outcome of a respective branch instruction;
providing a second indicator for a branch control instruction, said second indicator predicting whether a common branch target instruction associated with each of said plurality of branch instructions is likely to be needed for execution by the processor;
and
wherein target instruction loading within the processor is performed in accordance with an evaluation of said associated first indicator and said second indicator.

1 more element

A method of specifying execution of branch instructions within a program to be executed on a processor comprising the steps of:

(a) evaluating a plurality of branch instructions within the program before they are executed on the processor, each of said branch instructions being associated with a common branch target instruction;
and
(b) providing a setting for a plurality of branch prediction fields for said plurality of branch instructions before they are executed on the processor, each branch prediction field being associated with a respective branch instruction, said setting being provided in accordance with a prediction of whether said respective branch instruction is to be taken or is not to be taken;
and
(c) providing a branch target instruction prediction indicator before any of said plurality of branch instructions are executed on the processor, said branch target instruction prediction indicator being based on a consideration of each setting provided in step (b), and said branch target instruction prediction indicator being used for specifying to the processor whether said common branch target instruction is likely to be needed during execution of said plurality of branch instructions;
wherein a loading of branch target instructions by the processor can be specified by the program in advance so as to reduce expected branch latencies associated with executing the program.

3 more elements

Dependencies are inferred from the claim text.

Branch prediction and target instruction control for processor

Life of this patent

Branch prediction and target instruction control for processor

Life of this patent

Abstract

Claims21