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US 6,324,640 B1Granted
System and method for dispatching groups of instructions using pipelined register renaming
AssigneeInternational Business Machines Corporation
InventorsHung Qui Le, Hoichi Cheong
Life of this patent
Estimating the term…
Abstract
Within a superscalar processor, multiple groups of instructions are dispatched simultaneously to a plurality of execution units. A renaming mechanism is utilized to permit out-of-order execution of these instructions within the multiple groups. The renaming mechanism includes a rename table allocated for each dispatched group. A delay register is implemented between a portion of the dispatch queue dispatching a second one of the groups of instructions and a second one of the rename tables.
Claims14
A processor comprising:
- a plurality of execution units;
- a dispatch queue operable for concurrently dispatching a plurality of groups of instructions to be executed by the plurality of execution units;
- a plurality of rename tables, wherein a rename table is associated with each group, wherein a first one of the plurality of groups is mapped by a first one of the plurality of rename tables in a first cycle, and wherein a second one of the plurality of groups is mapped by a second one of the plurality of rename tables in a second cycle subsequent to the first cycle;
- and
- a delay register coupled between a portion of the dispatch queue dispatching the second one of the plurality of groups and the second one of the plurality of rename tables.
2 more elements
A processor comprising:
- a plurality of execution units;
- a dispatch queue operable for concurrently dispatching a plurality of groups of instructions to be executed by the plurality of execution units;
- and
- a plurality of rename tables, wherein a rename table is associated with each group, wherein a first and second one of the plurality of groups is allocated to a first one of the plurality of rename tables in a first cycle, and wherein the first one of the plurality of groups is additionally allocated to the second one of the plurality of rename tables in the first cycle, and wherein the second one of the plurality of groups is allocated to the second one of the plurality of rename tables in a second cycle subsequent to the first cycle.
1 more element
A processor comprising:
- a plurality of execution units;
- a dispatch queue operable for concurrently dispatching a plurality of groups of instructions to be executed by the plurality of execution units;
- and
- a plurality of rename tables, wherein a rename table is associated with each group, wherein a first one of the plurality of groups is mapped by a first one of the plurality of rename tables in a first cycle, and wherein a second one of the plurality of groups is mapped by a second one of the plurality of rename tables in a second cycle subsequent to the first cycle.
1 more element
A processor comprising:
- a plurality of execution units;
- a dispatch queue operable for concurrently dispatching a plurality of groups of instructions to be executed by the plurality of execution units;
- a plurality of rename tables, wherein a rename table is associated with each group;
- and
- a plurality of comparators for determining source-to-destination dependency for each instruction within each of the plurality of groups, wherein an output of the plurality of comparators is received by the dispatch queue.
2 more elements
In a processor, a method comprising the steps of:
- retrieving a plurality of instructions for execution by a plurality of execution units;
- grouping the plurality of instructions into first and second groups wherein each group contains a plurality of instructions;
- concurrently dispatching the first and second groups of instructions to the plurality of execution units;
- mapping the first group in a first rename table;
- mapping the second group in a second rename table;
- and
- delaying the mapping of the second group in the second rename table until a cycle subsequent to the cycle in which the first group is mapped in the first rename table.
4 more elements
In a processor, a method comprising the steps of:
- retrieving a plurality of instructions for execution by a plurality of execution units;
- grouping the plurality of instructions into first and second groups, wherein each group contains a plurality of instructions;
- concurrently dispatching the first and second groups of instructions to the plurality of execution units;
- and
- comparing destination architected pointers of an instruction in the first group with an instruction in the second group.
2 more elements
A processor comprising:
- an instruction cache operable for retrieving a plurality of instructions;
- a dispatch queue operable for grouping the plurality of instructions into first and second groups, wherein each group contains a plurality of instructions;
- a first rename table operable for mapping the first group;
- a second rename table operable for mapping the second group;
- a delay register coupled between the dispatch queue and the second rename table;
- an instruction issue queue coupled to the dispatch queue;
- and
- a plurality of execution units coupled to the issue queue, wherein the first and second groups of instructions are dispatched concurrently by the dispatch queue.
5 more elements
Dependencies are inferred from the claim text.