Instruction converting apparatus using parallel execution code
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsTaketo Heishi, Tetsuya Tanaka, Nobuo Higaki, Shuishi Takayama, Kensuke Odani
Life of this patent
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Abstract
A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1th unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.
Claims33
An instruction conversion apparatus that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions capable of being executed in parallel,
- the instruction conversion apparatus comprising:
- assigning means for successively assigning instructions in the instruction sequence to parallel execution codes;
- and
- control means for controlling the assigning means so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning means is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor;
- wherein the target processor includes (1) a fetch means for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, (3) decoding means, including s decoders that correspond to 1st to sth registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1st to sth registers, and (4) operation executing means, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders,
- the assigning means assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, one of an opcode and an operand of the long instruction to a uth (where u is any integer such that 1<u<s) unit field between the 1st unit field and the sth unit field, and only an operand of the long instruction to unit fields from a (u+l)th unit field to a (u+k−1)th unit field.
A processor, comprising:
- fetch means for successively fetching parallel execution codes that include a plurality of unit fields from outside the processor;
- a register set for storing a combination of a plurality of instructions included in at least two parallel execution codes that have been fetched by the fetch means;
- decoding means for decoding, when the combination of instructions stored in the register set satisfies predetermined restrictions, the instructions in the combination in parallel;
- and
- operation execution means for executing a plurality of operations in parallel in accordance with a decoding result of the decoding means;
- s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means,
- the decoding means including s decoders that correspond to 1st to sth registers in the s+k−1 registers and decode at least one opcode stored in any of the 1st to sth registers, and
- the operation executing means being connected to the s+k−1 registers and executing operations in accordance with a decoding result of the s decoders.
A recording medium storing executable code for a processor, the processor including (1) a fetch means for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, (3) decoding means, including s decoders that correspond to 1st to sth registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1st to sth registers, and (4) operation executing means, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders,
- the executable code stored on the recording medium being arranged such that at least one of an opcode and an operand of a long instruction having a word length of at least two but no more than k unit fields is arranged into to a uth (where u is any integer such that 1≦u≦s) unit field between the 1st unit field and the sth unit field, and only an operand of the long instruction is arranged in unit fields from a (u+1)th unit field to a (u+k−1)th unit field.
A computer-readable recording medium storing an instruction conversion program that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions that can be executed in parallel,
- the instruction conversion program comprising:
- an assigning step for successively assigning instructions in the instruction sequence to parallel execution codes;
- and
- a control step for controlling the assigning step so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning step is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor;
- wherein the target processor includes (1) a fetch means for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, (3) decoding means, including s decoders that correspond to 1st to sth registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1st to sth registers, and (4) operation executing means, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders,
- the assigning step assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, at least one of an opcode and an operand of the long instruction to a uth (where u is any integer such that 1<u<s) unit field between the 1st unit field the sth unit field, and only an operand of the long instruction to unit fields from a (u+1)th unit field to a (u+k−1)th unit field.
An instruction conversion apparatus that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions capable of being executed in parallel,
- the instruction conversion apparatus comprising:
- an assigning unit for successively assigning instructions in the instruction sequence to parallel execution codes;
- and
- a control unit for controlling the assigning unit so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning unit is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor;
- wherein the target processor includes (1) a fetch unit for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit, (3) a decoding unit, including s decoders that correspond to 1st to sth registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1st to sth registers, and (4) an operation executing unit, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders,
- the assigning unit assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, one of an opcode and an operand of the long instruction to a uth (where u is any integer such that 1<u<s) unit field between the 1st unit field and the sth unit field, and only an operand of the long instruction to unit fields from a (u+l)th unit field to a (u+k−1)th unit field.
A processor, comprising:
- a fetch unit for successively fetching parallel execution codes that include a plurality of unit fields from outside the processor;
- a register set for storing a combination of a plurality of instructions included in at least two parallel execution codes that have been fetched by the fetch unit;
- a decoding unit for decoding, when the combination of instructions stored in the register set satisfies predetermined restrictions, the instructions in the combination in parallel;
- and
- an operation execution unit for executing a plurality of operations in parallel in accordance with a decoding result of the decoding unit;
- s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit,
- the decoding unit including s decoders that correspond to 1st to sth registers in the s+k−1 registers and decode at least one opcode stored in any of the 1st to sth registers, and
- the operation executing unit being connected to the s+k−1 registers and executing operations in accordance with a decoding result of the s decoders.
A recording medium storing executable code for a processor, the processor including (1) a fetch unit for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit, (3) a decoding unit, including s decoders that correspond to 1st to sth registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1st to sth registers, and (4) an operation executing unit, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders,
- the executable code stored on the recording medium being arranged such that at least one of an opcode and an operand of a long instruction having a word length of at least two but no more than k unit fields is arranged into to a uth (where u is any integer such that 1<u<s) unit field between the 1st unit field and the sth unit field and the sth unit field, and only an operand of the long instruction is arranged in unit fields from a (u+1)th unit field to a (u+k−1)th unit field.
A computer-readable recording medium storing an instruction conversion program that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions that can be executed in parallel,
- the instruction conversion program comprising:
- an assigning step for successively assigning instructions in the instruction sequence to parallel execution codes;
- and
- a control step for controlling the assigning step so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning step is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor;
- wherein the target processor includes (1) a fetch unit for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit, (3) a decoding unit, including s decoders that correspond to 1st to sth registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1st to sth registers, and (4) an operation executing unit, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders,
- the assigning step assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, at least one of an opcode and an operand of the long instruction to a uth (where u is any integer such that 1<u<s) unit field between the 1st unit field the sth unit field, and only an operand of the long instruction to unit fields from a (u+1)th unit field to a (u+k−1)th unit field.
Dependencies are inferred from the claim text.