Methods for operating logical cache memory storing logical and physical address information

In a data processing system having a logical cache memory, a translation lookaside buffer and a main memory, the logical cache memory having a plurality of entries, each of the entries of the logical cache memory including data, physical address information, logical address information, shared information and address space identifier information, the translation lookaside buffer having a plurality of entries, each of the entries of the translation lookaside buffer including physical address information, logical address information, shared information and address space identifier information, a method comprising the steps of:

• A. initiating a memory access operation on a predetermined memory location based on logical address information and shared information associated with the memory access operation;
• B. selecting at least one entry of the logical cache memory based at least a portion of the logical address information of the memory access operation;
• C. determining if the memory access operation is for a shared physical address;
• D. if the memory access operation is for a shared physical address, then determining if there is a match between at least a portion of the logical address information of the memory access operation and at least a portion of the logical address information of the selected entry of the logical cache memory;
• E. if there is a match between the logical address information of the memory access operation and the logical address information of the selected entry of the logical cache memory, then accessing the data of the selected entry of the logical cache memory and completing the memory access operation;
• F. if there was not a match between the logical address information of the memory access operation and the logical address information of the selected entry of the logical cache memory, then accessing the translation lookaside buffer based on at least a portion of the logical address information of the memory access operation;
• G. if there is a match between the logical address information of the memory access operation and an entry of the translation lookaside buffer, then determining if there is match between at least a portion of the physical address information of the selected entry of the logical cache memory and physical address information of the entry of the translation lookaside buffer;
• and
• H. if there is a match between the physical address information of the selected entry of the logical cache memory and the physical address information of the entry of the translation lookaside buffer, then accessing the data of the selected entry of the logical cache memory and completing the memory access operation.

In a data processing system having a logical cache memory, a translation lookaside buffer and a main memory, the logical cache memory having a plurality of entries, each of the entries of the logical cache memory including data, physical address information, logical address information, validity information and address space identifier information, the translation lookaside buffer having a plurality of entries, each of the entries of the translation lookaside buffer including physical address information, logical address information, validity information and address space identifier information, a method comprising the steps of:

• A. initiating a memory access operation on a predetermined memory location based on logical address information associated with the memory access operation;
• B. selecting at least one entry of the logical cache memory based at least a portion of the logical address information of the memory access operation;
• C. determining if the validity information of the selected entry of the logical cache memory indicates that the selected entry of the logical cache memory is valid;
• D. if the selected entry of the logical cache memory is valid, then determining if there is a match between at least a portion of the logical address information of the memory access operation and at least a portion of the logical address information of the selected entry of the logical cache memory;
• E. if there is a match between the logical address information of the memory access operation and the logical address information of the selected entry of the logical cache memory, then accessing the data of the selected entry of the logical cache memory and completing the memory access operation;
• F. if there was not a match between the logical address information of the memory access operation and the logical address information of the selected entry of the logical cache memory, then accessing the translation lookaside buffer based on at least a portion of the logical address information of the memory access operation;
• G. if there is a match between the logical address information of the memory access operation and an entry of the translation lookaside buffer, then determining if there is match between at least a portion of the physical address information of the selected entry of the logical cache memory and physical address information of the entry of the translation lookaside buffer;
• and
• H. if there is a match between the physical address information of the selected entry of the logical cache memory and the physical address information of the entry of the translation lookaside buffer, then accessing the data of the selected entry of the logical cache memory and completing the memory access operation.