Division of memory into non-binary sized cache and non-cache areas

A tag-managed cache memory for a storage device having a plurality of blocks where each block is identified by a block address, the cache memory comprising:

• an interface for receiving a cache access having a block address specified therein;
• tag computation logic receiving the block address and generating a non-binary fractional result from the block address;
• and
• segmenting the result from the tag computation logic into a tag portion and an index portion.

A data storage system comprising:

• a comparatively high latency data storage mechanism;
• a comparatively low latency data storage mechanism, wherein the low latency mechanism comprises a binary-sized memory device having a non-binary-fraction-sized cache portion and a non-binary-fraction-sized non-cache portion;
• and
• a cache controller coupled to the low latency data storage mechanism and the high latency data storage mechanism and operable to cache data using only the cache portion.