Method and apparatus providing an improved PCI bus system

Abstract

A PCI-to-PCI bridge having a processor configured for performing various routing mode operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are known as “programmable decode modes.” In one programmable decode mode, private address spaces are defined for allowing two or more devices interconnected to a secondary PCI bus to communicate directly using private transactions. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. Another programmable decode mode is “intelligent” bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus.

Dependencies are inferred from the claim text.