Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion

An integrated circuit memory comprising:

• a memory storage array controlled and accessible by signals formatted in a two-level protocol;
• a clock generator coupled to the memory storage array, the clock generator operable to generate a clock signal;
• and
• an advanced input/output interface coupled to the memory storage array, the advanced input/output interface comprising:
• a bit compression circuit for receiving the clock signal and a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory, the bit compression circuit for converting the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol, the first multi-level protocol signal communicated out of the integrated circuit memory in synchronization with the clock signal;
• a bit decompression circuit for receiving a second signal in synchronization with the clock signal, the second signal formatted in the multi-level protocol, the bit decompression circuit for converting the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol, the second plurality of two-level protocol signals utilized within the integrated circuit memory, the bit decompression circuit comprising:
• a plurality of sample and hold comparators, each sample and hold comparator for sampling a voltage of the second multi-level protocol signal and comparing the sampled voltage against a respective reference voltage to output a respective data latch signal;
• and
• a decompression decoder circuit coupled to the sample and hold comparators, the decompression decoder circuit for decoding the data latch signals to output the second plurality of two-level protocol signals;
• and
• a voltage gain control circuit coupled to the bit compression circuit and the bit decompression circuit, the voltage gain control circuit for controlling gain on the first multi-level protocol signal.

A method for interfacing with an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol, the method comprising:

• generating a clock signal within the integrated circuit memory;
• converting a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory into a first signal formatted in a multi-level protocol;
• communicating the first multi-level protocol signal out of the integrated circuit memory in synchronization with the clock signal;
• receiving from outside the integrated circuit memory a second signal in synchronization with the clock signal, the second signal formatted in the multi-level protocol;
• and
• converting the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol, the second plurality of two-level protocol signals utilized within the integrated circuit memory, wherein converting the second multi-level protocol signal comprises:
• sampling a voltage of the second multi-level protocol signal;
• and
• comparing the sampled voltage against a reference voltage to output a data latch signal.

An integrated circuit device in communication with an integrated circuit memory having a memory storage array controlled and accessible by signals formatted in a two-level protocol, the integrated circuit device comprising:

• a memory controller;
• and
• an advanced input/output interface coupled to the memory controller, the advanced input/output interface comprising:
• a bit compression circuit for receiving a clock signal and a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit device, the bit compression circuit for converting the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol, the first multi-level protocol signal communicated out of the integrated circuit device to the integrated circuit memory in synchronization with the clock signal;
• a bit decompression circuit for receiving a second signal in synchronization with the clock signal, the second signal formatted in the multi-level protocol, the bit decompression circuit for converting the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol, the second plurality of two-level protocol signals utilized within the integrated circuit device, wherein the bit decompression circuit comprises a sample and hold comparator for sampling a voltage of the second multi-level protocol signal and holding the sampled voltage for comparison against a reference voltage;
• and
• a voltage gain control circuit coupled to the bit compression circuit and the bit decompression circuit, the voltage gain control circuit for controlling gain on the first multi-level protocol signal.

A memory architecture, comprising:

• a memory circuit that is accessible by signals formatted in a two-level protocol;
• a logic circuit accessible by signals formatted in the two-level protocol;
• the memory circuit and the logic circuit being separated within a common module by a communications path that exchanges data using a multi-level protocol;
• a first interface circuit associated with the memory circuit and being located along the communications path proximate to the memory circuit;
• a second interface circuit associated with the logic circuit and being located along the communications path proximate to the logic circuit;
• and
• the first and second interface circuits converting data between the multi-level protocol and the two-level protocol in synchronization with a clock signal to establish data exchange between the communications path and a respective memory circuit or logic circuit, wherein each of the first and second interface circuits comprises a respective sample and hold comparator for sampling voltages of signals formatted in the multi-level protocol and holding the sampled voltage for comparison against at least one reference voltage.

A method for interfacing with an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol, the method comprising:

• converting a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory into a first signal formatted in a multi-level protocol;
• communicating the first multi-level protocol signal out of the integrated circuit memory in synchronization with a clock signal;
• receiving from outside the integrated circuit memory a second signal in synchronization with the clock signal, the second signal formatted in the multi-level protocol;
• and
• converting the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol, the second plurality of two-level protocol signals utilized within the integrated circuit memory, wherein converting comprises:
• sampling a voltage of the second multi-level protocol signal;
• and
• comparing the sampled voltage against a reference voltage to output a data latch signal.