Process and device for computing a fourier transform having a “pipelined” architecture
AssigneeSTMicroelectronics S.r.l.
InventorJoel Cambonie
Life of this patent
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Abstract
For each input block of N data bits received as an input to a stage for computing a Fourier transform, only three quarters of the data bits of the input block are stored in a main storage. A Fourier transform computation is performed on the basis of the stored data and of the other data of the block. Only half of the data bits received are stored in an auxiliary storage. All the data bits of the input block are reconstructed from the contents of the main and auxiliary storage to obtain a reconstructed data block, which is temporally delayed with respect to the input block.
Claims21
A method for controlling a radix 4 processing stage of device heaving a pipelined architecture for computing a Fourier transform, the method comprising the steps of:
- receiving at least one input block comprising N data bits;
- storing 3N/4 data bits of the at least one input block in main storage comprising a random access memory;
- storing N/2 data bits of the at least one input block in auxiliary storage comprising a random access memory;
- performing a Fourier transform on the 3N/4 stored data bits and on a remaining N/4 data bits of the at least one input block;
- and
- reconstructing the N data bits of the at least one input block from the 3N/4 data bits and the N/2 data bits respectively stored in the main and auxiliary storages to generate a reconstructed data block temporally delayed with respect to the at least one input block.
A method for controlling a radix 4 processing stage for computing a Fourier transform in a device using orthogonal frequency division multiplex (OFDM) coding, the method comprising:
- receiving two successive input blocks separated by at least one guard interval, the at least one guard interval comprising guard data and each input block comprising N data bits;
- storing 3N/4 data bits of each input block in a main storage comprising a random access memory;
- storing N/2 data bits of each input block in an auxiliary storage comprising a random access memory;
- performing a Fourier transform on the 3N/4 stored data bits and on a remaining N/4 data bits of each input block;
- and
- reconstructing the N data bits of each input block from the 3N/4 data bits and the N/2 data bits respectively stored in the main and auxiliary storages to generate a reconstructed data block temporally delayed with respect to the two successive input blocks.
An electronic device having a pipelined architecture for computing a Fourier transform, the electronic device comprising:
- at least one processing stage with a radix equal to 4 receiving successive input blocks, each input block comprising N data bits, said at least one processing stage comprising
- a main storage circuit having a storage capacity equal to 3N/4 data bits,
- an auxiliary storage circuit having a storage capacity equal to N/2 data bits,
- a main processor performing a Fourier transform of elementary size equal to 4 on 3N/4 data bits stored in said main storage circuit and on a remaining N/4 data bits corresponding to an input block, and
- an auxiliary processor for reconstructing the N data bits of the input block from the 3N/4 data bits and N/2 data bits respectively stored in said main and auxiliary storage circuits for generating a reconstructed data block temporally delayed with respect to the input block.
Dependencies are inferred from the claim text.