US 6,324,504 B1 · System and method for bit interleaving of full-rate speech data

Abstract

A memory-efficient system and method for generating data blocks “on demand” for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

Claims7

Dependent claims

A method for bit reordering and frame interleaving for full rate speech in a Global System for Mobile communications (GSM) system, wherein said method comprises:

receiving two frames of forward error correction coded speech data;
storing each frame in a separate buffer(s);
transferring bits from said buffers to a Time Division Multiple Access (TDMA) block, wherein each bit transfer comprises:
determining the base address of one of said buffers;
calculating a word offset within one of said buffers;
calculating a bit offset within a selected word at said word offset;
and
transferring a selected bit at said bit offset to a bit position in said TDMA block.

5 more elements

A Global System for Mobile communications (GSM) transmitter module for converting forward error correction coded full-rate speech frames into Time Division Multiple Access (TDMA) data blocks, wherein said transmitter module comprises:

a memory configured to store said frames in a current frame buffer and a previous frame buffer, wherein said memory is further configured to provide data words from said buffers in response to word addresses;
an address generator coupled to receive a TDMA bit clock, wherein said address generator is configured to responsively select a base address for the current frame buffer for even cycles of the bit clock, wherein said address generator is configured to responsively select a base address for the previous frame buffer for odd cycles of the bit clock, wherein the address generator adds the selected base addresses to word offsets to produce said word addresses;
a bit position generator configured to generate said word offsets, wherein the bit position generator is further configured to generate bit offsets;
and
a multiplexer coupled to receive said data words and said bit offsets, wherein said multiplexer is configured to responsively provide a sequence of data bits.

2 more elements

Dependencies are inferred from the claim text.

System and method for bit interleaving of full-rate speech data

Life of this patent

System and method for bit interleaving of full-rate speech data

Life of this patent

Abstract

Claims7