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US 6,324,238 B1Granted
Bit counter stage, particularly for memories
AssigneeSTMicroelectronics S.r.l.
InventorLuigi Pascucci
Life of this patent
Estimating the term…
Abstract
A bit counter stage, particularly for memory addresses, including: a master storage circuit; a slave storage circuit which is connected to the master storage circuit; a circuit for enabling the transit of an external address in the master storage circuit; a circuit for enabling the connection between the slave storage circuit and the master storage circuit; a circuit for enabling the connection between the master storage circuit and the slave storage circuit; a circuit for calculating the product of the external address and of an input carry signal which arrives from a preceding counter stage; and a circuit for calculating an output carry signal on the basis of the external address and of the input carry signal.
Claims46
A bit counter stage, particularly for memory addresses, comprising:
- master storage means;
- slave storage means which are connected to said master storage means;
- means for enabling transit of an external address in said master storage means;
- means for enabling a first connection between said slave storage means and said master storage means;
- means for enabling a second connection between said master storage means and said slave storage means, the second connection connecting said slave storage means to said master storage means independently of said first connection connecting said slave storage means to said master storage means;
- means for calculating a product of said external address and of an input carry signal which arrives from a preceding counter stage;
- and
- means for calculating an output carry signal on the basis of said external address and of said input carry signal.
5 more elements
A counting method for a bit counter stage, particularly for addresses of a memory, comprising the steps of:
- receiving an external address;
- following a fast address latch enable signal, storing said external address in storage means and keeping said external address stored;
- in the presence of an address latch enable signal which is delayed with respect to said fast address latch enable signal, storing said external address in master storage means;
- following an increment signal and an input carry signal arriving from a preceding counter stage, calculating a new address which is incremented with respect to said external address and storing said new address in slave storage means which are connected to said master storage means;
- calculating, on the basis of said external address and of said input carry signal, an output carry signal, said output carry signal being an input signal for a subsequent counter stage;
- and
- following a signal for enabling a connection between said slave storage means and said master storage means, copying the content of said slave storage means into said master storage means.
4 more elements
A bit counter stage, particularly for memory addresses, comprising:
- master storage means;
- slave storage means which are connected to said master storage means;
- means for enabling transit of an external address in said master storage means;
- means for enabling a first connection between said slave storage means and said master storage means;
- means for enabling a second connection between said master storage means and said slave storage means;
- means for calculating a product of said external address and of an input carry signal which arrives from a preceding counter stage;
- and
- means for calculating an output carry signal on the basis of said external address and of said input carry signal;
- wherein said means for calculating the product of said external address and of said input carry signal comprise a first circuit path and a second circuit path, each path being enabled by a respective pass gate which is driven by said input carry signal and by an inverted equivalent thereof, inverter means being connected in output to said master storage means, said first circuit path beginning upstream of said inverter means and said second circuit path beginning downstream of said inverter means.
6 more elements
A bit counter stage, particularly for memory addresses, comprising:
- master storage means;
- slave storage means which are connected to said master storage means;
- means for enabling transit of an external address in said master storage means;
- means for enabling a first connection between said slave storage means and said master storage means;
- means for enabling a second connection between said master storage means and said slave storage means;
- means for calculating the product of said external address and of an input carry signal which arrives from a preceding counter stage;
- and
- means for calculating an output carry signal on the basis of said external address and of said input carry signal;
- wherein said means for calculating the output carry signal comprise a pass gate which is driven by said input carry signal and by an inverted equivalent thereof, and by a field effect transistor, said pass gate being connected to the gate terminal of said field effect transistor.
6 more elements
A bit counter stage, particularly for memory addresses, comprising:
- master storage means;
- slave storage means which are connected to said master storage means;
- means for enabling transit of an external address in said master storage means;
- means for enabling a first connection between said slave storage means and said master storage means;
- means for enabling a second connection between said master storage means and said slave storage means;
- means for calculating the product of said external address and of an input carry signal which arrives from a preceding counter stage;
- means for calculating an output carry signal on the basis of said external address and of said input carry signal;
- means for temporary storage of said external address;
- and
- means for selectively connecting said means for temporary storage and said master storage means.
7 more elements
A bit counter stage of a counter, comprising:
- a master storage element;
- a slave element;
- circuitry for storing an externally generated data bit value in the master storage element;
- a first circuit path selectively coupling the master storage element and the slave storage element;
- a second circuit path selectively coupling the master storage element and the slave storage element, the second circuit path coupling the master and slave storage elements independently of the first circuit path coupling the master and slave storage elements;
- circuitry for generating a data output signal based upon the state of the master storage element;
- and
- circuitry for generating a carry output signal based upon the state of the master storage element.
5 more elements
A method of operating a bit counter stage having a master storage element and a slave storage element, comprising:
- maintaining a data value in the master storage element during a first time period;
- updating, during at least a portion of the first time period, the slave storage element with a data value based upon the data value maintained in the master storage element and upon a carry input signal;
- following the first time period, updating the master storage element with the data value stored in the slave storage element during a second time period;
- and
- following the second time period, generating a data output signal based upon the value stored in the master storage element during the second time period, the data output signal corresponding to an incremented representation of the data value maintained in the master storage element during the first time period.
2 more elements
Dependencies are inferred from the claim text.