Phase detector arrangement
AssigneeTelefonaktiebolaget LM Ericsson (publ)
InventorMats Bladh
Life of this patent
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Abstract
A phase detector arrangement for use in a phase locked loop circuit recovers clock and data pulses from a data stream comprising Return to Zero (RZ) signals including digital data. The arrangement includes a comparator, a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector includes a phase position indicator which is activated by each incoming data pulse in the output line of the comparator. A method for recovering clock and data pulses includes the steps of monitoring the data pulses in each output line of the comparator and controlling the voltage controlled oscillator in relation to both edges of each data pulse, for clocking data synchronously with the pulse.
Claims22
A phase detector arrangement for use in a phase locked loop circuit, for recovery of clock and data pulses from a data stream comprising Return to Zero (RZ) signals comprising digital data, said arrangement comprising a comparator, a phase detector, a loop filter and a voltage controlled oscillator, wherein the phase detector comprises a phase position indicator, having at least one tristate buffer, which is activated by each incoming data pulse in an output line of the comparator, said phase position indicator being adapted to control the voltage controlled oscillator in relation to both edges of each data pulse, for clocking data synchronously with said data pulse, and wherein
- the phase position indicator output is connected in series via a resistor to an earth-connected capacitor, for integration of the output signal with reference to the duration of each data pulse to a mean value which corresponds to a phase position between the data pulse and the clock signal.
A method for recovery of clock and data pulses from a data stream comprising digital signals being received by a comparator, comprising the steps of
- monitoring the data pulses in at least one output line of the comparator,
- controlling a voltage controlled oscillator in relation to both edges of each data pulse using a phase detector having at least one tristate buffer coupled to a corresponding output line of the comparator, for synchronizing with said data pulse, and
- integrating an input signal coupled to said at least one tristate buffer and controlled by each output line of the comparator with reference to the duration of each pulse to a mean value which corresponds to the phase position between each data pulse and the clock signal.
A phase detector arrangement for use in a phase locked loop circuit, for recovery of clock and data pulses from a data stream comprising Return to Zero (RZ) signals comprising digital data, said arrangement comprising a comparator, a phase detector, a loop filter and a voltage controlled oscillator, wherein the phase detector comprises a phase position indicator, having at least one analog switch, which is activated by each incoming data pulse in the output of the comparator, said phase position indicator being adapted to control the voltage controlled oscillator in relation to both edges of each data pulse, for clocking data synchronously with said data pulse, and wherein
- the phase position indicator output is connected in series via a resistor to an earth-connected capacitor, for integration of the output signal with reference to the duration of each data pulse to a mean value which corresponds to a phase position between the data pulse and the clock signal.
A method for recovery of clock and data pulses from a data stream comprising digital signals being received by a comparator, comprising the steps of:
- monitoring the data pulses in at least one output line of the comparator;
- controlling a voltage controlled oscillator in relation to both edges of each data pulse using a phase detector having at least one analog switch coupled to a corresponding output line of the comparator, for synchronizing a clock signal with said data pulse;
- and
- integrating an input signal coupled to said at least one analog switch and controlled by each output line of the comparator with reference to the duration of each pulse to a mean value which corresponds to the phase position between each data pulse and the clock signal.
Dependencies are inferred from the claim text.