Viterbi decoder
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorYukihiro Sasagawa
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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorYukihiro Sasagawa
Estimating the term…
A Viterbi decoder is provided in which conventional RAMs or the like is used for a path metric memory and a path selection signal memory, and the number of times the memory is accessed in an ACS operation and a trace-back operation is reduced, thus achieving a reduction in power consumption and an increase in speed of processing operations. In this Viterbi decoder, based on branch metrics calculated from input codes by a branch metric operation section, an add-compare-select (ACS) operation section calculates path metrics of respective states by time-sharing processing. The path metrics sequentially calculated by the ACS operation section are delayed temporarily by a path metric permutation section and are permutated to have different time series from those of the path metrics calculated by the ACS operation section, which then are stored in a path metric memory.
A Viterbi decoder, comprising:
A Viterbi decoder, comprising:
A Viterbi decoder, comprising:
A Viterbi decoder, comprising:
Dependencies are inferred from the claim text.