A digital receiver for receiving a digital input signal converted by a given sampling rate, comprising:
- a plurality of delays connected in series for sequentially delaying said digital input signal, wherein a first of said plurality of delays receives said digital input signal;
- a first branch, comprising:
- a first down-sampler having an input that receives said digital input signal for lowering a sampling rate of said digital input signal;
- a first plurality of down-samplers for lowering a sampling rate of said sequentially delayed digital input signal, wherein each of said plurality of down-samplers receives a signal from one of said plurality of delays;
- a first filter for selecting a signal of a desired channel from a signal received from said first down-sampler;
- a first plurality of filters for selecting signals of a desired channel from signals received from said first plurality of down-samplers, wherein each of said first plurality of filters receives a signal from one of said first plurality of down-samplers, and wherein each of said first plurality of filters is therein associated with said one of said first plurality of down-samplers;
- and
- a first plurality of adders connected in series, wherein each of said plurality of adders is associated with one of said first plurality of delays;
- wherein each of said first plurality of down-samplers and associated filters is connected between an output of one of said first plurality of delays and an input of said associated adder, and a first adder of said first plurality of adders receives its signal from said first filter;
- a second branch, comprising:
- a second down-sampler having an input that receives said digital input signal for lowering a sampling rate of said digital input signal;
- a second filter for selecting a signal of a desired channel from a signal received from said second down-sampler;
- a second plurality of down-samplers for lowering a sampling rate of said sequentially delayed digital input signal, wherein each of said second plurality of down-samplers receives a signal from one of said second plurality of delays;
- a second plurality of filters for selecting signals of a desired channel from signals received from said plurality of down-samplers, wherein each of said second plurality of filters receives a signal from one of said second plurality of down-samplers, and wherein each of said second plurality of filters is therein associated with said one of said second plurality of down-samplers;
- and
- a second plurality of adders connected in series, wherein each of said second plurality of adders is associated with one of said second plurality of delays;
- wherein each of said second plurality of down-samplers and associated filters is connected between an output of one of said second plurality of delays and an input of said associated adder, and a first adder of said second plurality of adders receives its signal from said second filter;
- a first multiplier for multiplying an output of a last adder of said first branch by a first multiplying factor;
- a second multiplier for multiplying an output of a last adder of said second branch by a second multiplying factor;
- a second adder for adding outputs of said first and second multipliers to each other to generate a signal corresponding to an I channel;
- a third adder for generating a difference between outputs of said first and second multipliers;
- and
- a third multiplier for multiplying an output of said third adder by a complex number to generate a signal corresponding to a Q channel.