Scalable method for generating long codes using gold sequences
AssigneesSony Corporation, Sony Electronics Inc.
InventorMohit K. Prasad
Life of this patent
Estimating the term…
Abstract
A scalable method and system for generating a 3X long code sequence for use in a CDMA communication system uses Gold sequences. A preferred pair of 1X long code sequences both running at 1.2288 Mchips/s are used to generate the 3X sequence. The 3X sequence so generated is a pseudo-random sequence with well defined auto-correlation and cross-correlation properties. Because the method is scalable it is easily scaled to generate other long code e.g. 6X, 9X, and 12X sequences.
Claims6
A method for generating a KX long code sequence for use in a CDMA communication system, where K is an integer multiple of 3, the method comprising:
- (i) generating a preferred pair of sequences b(d) and b′(D) each being of length N and each being a 1X long code sequence;
- wherein N=2n−1
- (ii) forming sequence [b(d)+b′(D)] by modulo 2 adding sequences b(d) and b′(D);
- (iii) delaying the sequence b′(D) by a predefined amount (K−3) times to thereby form (K−3) delayed sequences of sequence b′(D);
- (iv) modulo 2 adding the sequence b(d) to each of the (K−3) delayed sequences formed in step (iii)
- (v) generating a KX clock signal whose frequency is K times that of a clock signal used to generate the 1X sequences b(d) and b′(d);
- and
- (vi) recurrently for each K transitions of the KX clock setting a bit of the KX sequence to an associated one of the bits respectively of sequences b(D)—and [b(D)+b′(d)] and b′(D) and the (K−3) sequences formed in step (iv) sequentially.
A long code sequence generator for generating a KX long code sequence for use in a CDMA communication system, the long code generator comprising:
- (i) A pair of 1X long code sequence generators for generating a preferred pair of sequences b(d) and b′(D) each being of length N wherein N=2n−1
- (ii) (K−3) delay elements each for delaying the sequence b′(D) to thereby form (K−3) delayed sequences of sequence b′(D)
- (iii) (K−2) modulo 2 adders each for modulo 2 adding the sequence b(d) to each one of the b′(D) and the (K−3) delayed sequences formed in step (ii)
- (vi) A multiplexer having K input terminals and an output terminal, wherein each input terminal of the multiplexer receives a signal form a different one of the sequences b(D) [b(D)+b′(d)] b′(D) and the (K−3) sequences formed in step (iii)
- (iv) A KX clock signal generator having a frequency which is K times that of a clock signal used for generating the 1X sequences b(d) and b′(d);
- wherein during each K transitions of the KX clock a different one of the N terminals of the multiplexer is sequentially selected.
Dependencies are inferred from the claim text.