Pulse width detection

A semiconductor circuit comprising:

• operational circuitry for producing a pulse having a pulse width;
• a plurality of delay elements enabled and disabled in parallel by the pulse, the plurality of delay elements being adapted to provide at least portions of the pulse to a plurality of delay element output ports at a plurality of different times;
• and
• a decoder coupled to the plurality of delay element output ports and responsive to the pulse at the plurality of delay element output ports to provide a signal indicative of a window of time durations that includes the pulse width.

A semiconductor circuit comprising:

• circuitry for producing a pulse;
• a plurality of n delay elements enabled and disabled in parallel by the pulse, each delay element adapted to transmit the pulse from an input to an output, the plurality of n delay elements configured to transmit the pulse to corresponding outputs of the plurality of n delay elements at different times;
• and
• n−1 detectors each having a detector input coupled to an input of a corresponding one of the plurality of n delay elements, each detector adapted to set a state of a detector output to a predetermined state from a plurality of states in response to receiving a portion of the pulse.

A semiconductor circuit comprising:

• circuitry for producing a pulse;
• a plurality of n delay elements enabled and disabled in parallel by the pulse, each delay element adapted to transmit the pulse from an input to an output, the plurality of n delay elements configured to transmit the pulse to corresponding outputs of the plurality of n delay elements at different times;
• and
• n−1 detectors each having a detector input coupled to an input of a corresponding one of the plurality of n delay elements, each detector adapted to set a state of a detector output to a predetermined state from a plurality of states in response to receiving a portion of the pulse;
• wherein each detector output is selectively coupled to an output pin of the circuit;
• and;
• wherein the input port of each of the plurality of n delay elements is connected in common.

A semiconductor circuit comprising:

• circuitry for producing a pulse;
• a plurality of n delay elements enabled and disabled in parallel by the pulse, each delay element adapted to transmit the pulse from an input to an output, the plurality of n delay elements configured to transmit the pulse to corresponding outputs of the plurality of n delay elements at different times;
• n−1 detectors each having a detector input coupled to an input of a corresponding one of the plurality of n delay elements, each detector adapted to set a state of a detector output to a predetermined state from a plurality of states in response to receiving a portion of the pulse;
• further comprising another detector having a detector input coupled to the input of a first one of the plurality of n delay elements;
• and further comprising another detector having a detector input coupled to the output of a last one of the plurality of n delay elements.

A semiconductor circuit comprising:

• circuitry for producing a pulse;
• a plurality of n delay elements serially coupled and adapted to be enabled and disabled in parallel by leading and trailing edges, respectively, of the pulse, each delay element adapted to delay the pulse as it is transmitted between a delay element input and a delay element output of that delay element;
• and
• a plurality of n latches each having a latch input coupled to a corresponding delay element input, each latch adapted to set a state of a latch output port to a first predetermined state in response to receiving a portion of the pulse at the latch input, a selected one of the plurality of n latches having a latch reset coupled to the output of a last one of the plurality of n delay elements and being adapted to set the state of that latch to a second predetermined state in response to receiving a portion of the pulse at the latch reset.

A semiconductor circuit comprising:

• circuitry for producing a pulse;
• a plurality of n delay elements serially coupled and adapted to be enabled and disabled in parallel by leading and trailing edges, respectively, of the pulse, each delay element adapted to delay the pulse as it is transmitted between a delay element input and a delay element output of that delay element;
• and
• a plurality of n latches each having a latch input coupled to a corresponding delay element input, each latch adapted to set a state of a latch output port to a first predetermined state in response to receiving a portion of the pulse at the latch input, a selected one of the plurality of n latches having a latch reset coupled to the output of a last one of the plurality of n delay elements and being adapted to set the state of that latch to a second predetermined state in response to receiving a portion of the pulse at the latch reset, wherein the selected one of the plurality of n latches is a first one of the plurality of n latches.

A semiconductor circuit comprising:

• circuitry for providing a signal including a pulse;
• a plurality of n delay elements having enable ports coupled in parallel, each one of the plurality of n delay elements adapted to be activated and deactivated by a first edge and a second edge, respectively, of the pulse received at the corresponding enable port, each delay element adapted to transmit the pulse from a delay element input port to a delay element output port delayed by a corresponding time delay;
• and
• a plurality of n−1 latches each having a latch input port coupled to a corresponding delay element input port and adapted to provide a DC signal to a latch output port in response to receiving the first edge of the pulse at the latch input port.

A semiconductor circuit comprising:

• operational circuitry for providing a signal including a pulse;
• a delay element including a delay element input port and a delay element enable port both selectively coupled to the operational circuitry, the delay element being enabled and disabled by the pulse incident at the enable port, the delay element configured to receive the pulse at the delay element input port at a first time and provide the pulse to a delay element output port at a second time, later than the first time;
• and
• a latching element including a latching element input port coupled to the delay element output port, the latching element output port being selectively coupled to an output contact of the semiconductor circuit, the latching element being configured to provide a DC signal to the output port of the latching element in response to receiving at least a portion of the pulse at an input port of the latching element.

A system for testing a semiconductor circuit, the system comprising:

• a semiconductor circuit comprising:
• circuitry for producing a pulse;
• a plurality of n delay elements enabled and disabled in parallel by the pulse and adapted to deliver the pulse to corresponding outputs of the plurality of n delay elements at different output times defining time duration windows having corresponding timespans;
• and
• a plurality of n−1 detectors each having a detector input coupled to an input of a corresponding one of the plurality of n delay elements, each detector adapted to set a state of a detector output to a predetermined state from a plurality of states in response to receiving a portion of the pulse;
• and
• a tester having an operational frequency that is lower than a shortest one of the timespans and being adapted to detect the predetermined state.