Memory device having a variable data output length
AssigneeRambus Inc.
InventorsMichael Farmwald, Mark Horowitz
Life of this patent
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Abstract
A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing block size information to the memory device, synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes issuing a first read request to the memory device, wherein the memory device receives the first read request synchronously with respect to a transition of the external clock signal.
Claims39
A method of operation of a synchronous memory device, wherein the memory device includes an array of memory cells, the method of operation comprises:
- receiving an external clock signal;
- receiving block size information, wherein the block size information defines an amount of data to be output by the memory device in response to a first operation code;
- sampling the first operation code synchronously with respect to the external clock signal wherein the first operation code instructs the memory device to perform a read operation;
- and
- outputting the amount of data in response to the first operation code.
A method of controlling a synchronous memory device by a controller, wherein the memory device includes an array of memory cells, the method of controlling the memory device comprises:
- issuing block size information to the memory device synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device;
- and
- issuing a first operation code to the memory device synchronously with respect to the external clock signal, wherein the first operation code instructs the memory device to perform a read operation.
A synchronous dynamic random access memory device having at least one memory section including a plurality of memory cells, the memory device comprising:
- clock receiver circuitry to receive an external clock signal;
- input receiver circuitry, including a first plurality of input receivers to sample block size information synchronously with respect to the external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a first operation code;
- and
- a plurality of output drivers to output the amount of data in response to the first operation code.
Dependencies are inferred from the claim text.