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US 6,324,118 B1Granted
Synchronous semiconductor memory device having improved operational frequency margin at data input/output
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
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Abstract
A synchronous semiconductor memory device includes a latch for temporarily storing data to be output to the outside, and a latch temporarily storing data input from the outside. The latches operate based on an internal clock when exchanging data with internal memory block, and operate based on a clock in phase with an external clock when exchanging data with the outside.
Claims6
A synchronous semiconductor memory device, comprising:
- an input/output terminal for inputting/outputting data;
- an input/output circuit exchanging said data with said input/output terminal,
- said input/output circuit including
- a first data holding circuit holding first data, and
- a second data holding circuit holding second data;
- a data bus exchanging said data with said input/output circuit;
- and
- an internal circuit performing an operation of reading/storing said data from/to said data bus.
5 more elements
Dependencies are inferred from the claim text.