Method of selecting a memory access line and an access line decoder for performing the same

A method for selecting an access line to a matrix of memory cells with serial data access, one or more access lines selected from the group of access lines consisting of bit lines and word lines, the method comprising the steps of:

• a) associating a line code of p bits to one or more access lines forming a group (AL0-AL7);
• b) activating all the access lines of the group (AL0-AL7);
• c) receiving, via a serial data input (DI), a bit (Ai) of determined rank of the access line to select;
• and
• d) deactivating one or more access lines as a function of the value of the bit (Ai) received, which the line code presents a bit of rank i of value different from that of the bit (Ai) received;
• and
• e) repeating the steps c and d for p times successively, for each of the bits of the line code received via the serial data input to a matrix of memory cells, such that at the end of p iterations of the steps of c and d, only the access line to be selected remains activated.

An access line decoder for selecting an access line to a matrix of memory cells with serial data access, comprising:

• one or more access lines selected from the group of access lines consisting of bit lines and word lines;
• a plurality of latches, each coupled to one or more access lines, of a group of access lines, wherein a line code is associated to the one or more access lines, each latch comprising:
• a switching element to impose a non-zero voltage potential on the access line when the latch is in an activated state and a zero voltage potential when the latch is in a deactivated state;
• an activation element for setting the latch to the activated state;
• and
• a deactivation elements for setting the latch to a deactivated state as a function of the line code which is specific to one or more access lines and as a function of one or more selection signals received by the deactivation element;
• means for setting all the latches to the activated state;
• and
• means for generating the one or more selection signals as a function of the line code received via a serial data to a matrix of memory cells.