Semiconductor memory device with burst mode access
AssigneeSamsung Electronics Co., Ltd.
InventorByeng-Sun Choi
Life of this patent
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Abstract
A data sensing control circuit according to the present invention is provided in a semiconductor memory device with a burst access mode. The data sensing control circuit generates sensing control signals for data sensing operation by use of a transition information of an address bit signal synchronized with a read enable clock signal and used for a bank selection. According to such a data sensing control scheme, no sensing of each sensing period is performed when the read enable clock signal transitions. Therefore, a power noise (or input/output noise) issued at data-out does not affect the data sensing operation of the semiconductor memory device having the burst access mode.
Claims13
A semiconductor memory device comprising:
- a memory array having first and second memory banks, each bank comprising a plurality of memory cells for storing multi-level data;
- a counter circuit for receiving externally applied address bit signals, generating an internal address based on the address bit signals, and incrementing the internal address in synchronization with a read enable clock signal;
- a data sensing control circuit that generates a set of data sensing control signals and bank selection signaling, based on the internal address supplied by the counter circuit;
- and
- a data reading circuit operated responsive to the data sensing control signals, capable of sensing multi-level data from the first and second memory banks alternately, wherein the data reading circuit holds the multi-level data sensed from one of the memory banks and, at the same time, senses multi-level data from the other of the memory banks during a data sensing operation timed such that data sensing during a read enable clock signal transition is avoided.
A semiconductor memory device comprising:
- a memory array having first and second memory banks, each bank comprising a plurality of memory cells, the memory array having a burst access mode wherein data from one memory bank is output while data from the other memory bank is sensed;
- and
- a data sensing control circuit for generating data sensing control signals for the memory array, the data sensing control signals synchronized to a read enable clock signal during burst access mode operation, such that a data-sensing operation occurs between two successive read enable clock signals.
A method of operating a memory device comprising memory cells for storing multi-level data, the method comprising the steps of:
- reading a plurality of data values stored in the memory device into an output buffer in parallel;
- outputting the plurality of data values serially from the output buffer in response to consecutive read enable clock signals;
- and,
- during the outputting step, sensing a second plurality of data values stored in the memory device, wherein the sensing step is synchronized with the read enable clock signals, thereby avoiding data sensing during a read enable clock signal transition.
Dependencies are inferred from the claim text.