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US 6,324,114 B1Granted
Semiconductor memory device using a plurality of semiconductor memory chips mounted in one system and a semiconductor memory system using a plurality of semiconductor memory devices
AssigneeKabushiki Kaisha Toshiba
InventorToshihiko Himeno
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device has an address input circuit system capable of specifying a virtual memory space having a capacity larger than the actual storage capacity and a decoder system and sets the output terminal of a data output circuit system into a high impedance state when an address other than the previously specified addresses for the real memory space is specified. A plurality of semiconductor memory devices described above are used to construct a semiconductor memory system by commonly connecting corresponding ones of all of the input/output signal pins in parallel.
Claims72
A semiconductor memory device comprising:
- a plurality of first input circuits supplied with a first address signal for specifying a real memory space of a memory cell array;
- at least a second input circuit supplied with a second address signal for specifying a virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- real memory position setting circuit setting a position of an real memory space in the virtual memory space;
- determination circuit determining whether or not an address designated by the second address signal coincides with the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- address decoder circuit decoding an output signal of said plurality of first input circuits and accessing the memory cell array when said determination circuit determines that the real memory space is accessed;
- and
- output circuit outputting data read out from the memory cell array.
4 more elements
A semiconductor memory device comprising:
- a plurality of first input circuits supplied with a first address signal for specifying a real memory space of a memory cell array;
- at least a second input circuit supplied with a second address signal for specifying a virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- counting circuit latching the first and second address signals input to said first and second input circuits and sequentially counting up the address signals;
- real memory position setting circuit setting a position of the real memory space in the virtual memory space;
- determination circuit determining whether or not an address designated by the second address signal coincides with the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- address decoder circuit decoding an output signal of said pluarality of first input circuits and accessing the memory cell array when said determination circuit determines that the real memory space is accessed;
- and
- output circuit for outputting data read out from the memory cell array;
- wherein the second address signal is counted up by said counting circuit irrespective of the setting contents of said real memory position setting circuit and an output signal corresponding to the second address signal is controlled to be inverted or not according to the setting contents of said real memory position setting circuit before a count output of said counting circuit is input to said address decoder circuit.
6 more elements
A semiconductor memory device comprising:
- an input buffer supplied with a first address signal for specifying a real memory space of a memory cell array;
- real memory position setting circuit setting a position of the real memory space in a virtual memory space having a capacity larger than a storage capacity of an memory cell array;
- an input switching circuit supplied with a second address signal for specifying the virtual memory space, for inverting the second address signal or keeping the second address signal non-inverted to form an internal address signal according to the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- an address decoder decoding an output signal from said input buffer and the internal address signal output from said input switching circuit to access the memory cell array;
- an output buffer outputting data read out from the memory cell array;
- and
- a chip address decoder circuit decoding the internal address signal output from said input switching circuit and setting an output terminal of said output buffer into a high impedance state when the real memory space is not accessed.
4 more elements
A semiconductor memory device comprising:
- an input buffer supplied with a first address signal for specifying a real memory space of a memory cell array;
- a real memory position setting circuit setting a position of the real memory space in a virtual memory space having a capacity larger than a storage capacity of an memory cell array;
- an input switching circuit supplied with a second address signal for specifying the virtual memory space, for inverting the second address signal or keeping the second address signal non-inverted to form an internal address signal according to the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- an address decoder decoding an output signal from said input buffer and the internal address signal output from said input switching circuit to access the memory cell array;
- an output buffer outputting data read out from the memory cell array;
- and
- a chip address decoder circuit decoding the internal address signal output from said input switching circuit and setting a chip into a stand-by state when the real memory space is not accessed.
4 more elements
A semiconductor memory device comprising:
- an input buffer supplied with a first address signal for specifying a real memory space of a memory cell array;
- a real memory position setting circuit setting a position of the real memory space in a virtual memory space having a capacity larger than a storage capacity of an memory cell array;
- an input switching circuit supplied with a second address signal for specifying the virtual memory space, for inverting the second address signal or keeping the second address signal non-inverted to form an internal address signal according to the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- an address decoder decoding an output signal from said input buffer and the internal address signal output from said input switching circuit to access the memory cell array;
- an output buffer outputting data read out from the memory cell array;
- and
- a chip address decoder circuit decoding the internal address signal output from said input switching circuit and setting a chip into a stand-by state and setting an output terminal of said output buffer into a high impedance state when the real memory space is not accessed.
4 more elements
A semiconductor memory system comprising:
- a plurality of semiconductor memory devices mounted with corresponding ones of all of input/output signal pins commonly connected in parallel;
- each of said plurality of semiconductor memory devices including:
- a plurality of first input circuits supplied with a first address signal for specifying a real memory space of a memory cell array;
- at least a second input circuit supplied with a second address signal for specifying a virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- real memory position setting circuit setting a position of the real memory space in the virtual memory space;
- determination circuit determining whether or not an address designated by the second address signal coincides with the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- address decoder circuit decoding an output signal of said plurality of first input circuit and accessing the memory cell array when said determination circuit determines that the real memory space is accessed;
- and
- output circuit outputting data read out from the memory cell array;
- wherein said output circuit is set into a high impedance state when said determination circuit determines that the real memory space is not accessed.
7 more elements
A semiconductor memory system comprising:
- a plurality of semiconductor memory devices mounted with corresponding ones of all of input/output signal pins commonly connected in parallel;
- each of said plurality of semiconductor memory devices including:
- plurality of first input circuits supplied with a first address signal for specifying a real memory space of a memory cell array;
- at least a second input circuit supplied with a second address signal for specifying a virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- real memory position setting circuit setting a position of the real memory space in the virtual memory space;
- determination circuit determining whether or not an address designated by the second address signal coincides with the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- address decoder circuit decoding an output signal of said plurality of first input circuits and accessing the memory cell array when said determination circuit determines that the real memory space is accessed;
- and
- output circuit outputting data read out from the memory cell array;
- wherein a semiconductor memory chip is set into a stand-by state when said determination circuit determines that the real memory space is not accessed.
7 more elements
A semiconductor memory system comprising:
- a plurality of semiconductor memory devices mounted with corresponding ones of all of input/output signal pins commonly connected in parallel;
- each of said plurality of semiconductor memory devices including:
- plurality of first input circuits supplied with a first address signal for specifying a real memory space of a memory cell array;
- at least a second input circuit supplied with a second address signal for specifying a virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- real memory position setting circuit for setting a position of the real memory space in the virtual memory space;
- determination circuit determining whether or not an address designated by the second address signal coincides with the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- address decoder circuit decoding an output signal of said plurality of first input circuit and accessing the memory cell array when said determination circuit determines that the real memory space is accessed;
- and
- output circuit outputting data read out from the memory cell array;
- wherein a semiconductor memory chip is set into a stand-by state and said output circuit is set into a high impedance state when said determination circuit determines that the real memory space is not accessed.
7 more elements
A semiconductor memory system comprising:
- a plurality of semiconductor memory devices mounted with corresponding ones of all of input/output signal pins commonly connected in parallel;
- each of said plurality of semiconductor memory devices including:
- an input buffer supplied with a first address signal for specifying a real memory space of a memory cell array;
- real memory position setting circuit setting a position of the real memory space in virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- an input switching circuit supplied with a second address signal for specifying the virtual memory space, for inverting the second address signal or keeping the second address signal non-inverted to form an internal address signal according to the position of the real memory space in the virtual memory space set by said real memory position setting means;
- an address decoder decoding an output signal from said input buffer and the internal address signal output from said input switching circuit to access the memory cell array;
- an output buffer outputting data read out from the memory cell array;
- and
- a chip address decoder circuit decoding the internal address signal output from said input switching circuit and setting an output terminal of said output buffer into a high impedance state when the real memory space is not accessed.
6 more elements
A semiconductor memory system comprising:
- a plurality of semiconductor memory devices mounted with corresponding ones of all of input/output signal pins commonly connected in parallel;
- each of said plurality of semiconductor memory devices including:
- an input buffer supplied with a first address signal for specifying a real memory space of a memory cell array;
- real memory position setting means for setting a position of the real memory space in an virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- an input switching circuit supplied with a second address signal for specifying the virtual memory space, for inverting the second address signal or keeping the second address signal non-inverted to form an internal address signal according to the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- an address decoder decoding an output signal from said input buffer and the internal address signal output from said input switching circuit to access the memory cell array;
- an output buffer outputting data read out from the memory cell array;
- and
- a chip address decoder circuit decoding the internal address signal output from said input switching circuit and setting a semiconductor memory chip into a stand-by state when the real memory space is not accessed.
6 more elements
A semiconductor memory system comprising:
- a plurality of semiconductor memory devices mounted with corresponding ones of all of input/output signal pins commonly connected in parallel;
- each of said plurality of semiconductor memory devices including:
- an input buffer supplied with a first address signal for specifying a real memory space of a memory cell array;
- real memory position setting circuit setting a position of the real memory space in virtual memory space having a capacity larger than a storage capacity of the memory cell array;
- an input switching circuit supplied with a second address signal for specifying the virtual memory space, for inverting the second address signal or keeping the second address signal non-inverted to form an internal address signal according to the position of the real memory space in the virtual memory space set by said real memory position setting circuit;
- an address decoder decoding an output signal from said input buffer and the internal address signal output from said input switching circuit to access the memory cell array;
- an output buffer outputting data read out from the memory cell array;
- and
- a chip address decoder circuit decoding the internal address signal output from said input switching circuit and setting a semiconductor memory chip into a stand-by state and setting an output terminal of said output buffer into a high impedance state when the real memory space is not accessed.
6 more elements
A semiconductor memory device comprising:
- a plurality of semiconductor memory chips, each of said semiconductor memory chips including N input buffers, where N is a positive integer, M input switching circuits, where M is a positive integer, and a plurality of output buffers, said M input switching circuits being supplied with predetermined signals;
- N input signal lines respectively coupled to the N input buffers of each of said semiconductor memory chips;
- M input signal lines respectively coupled to the M input buffers of each of said semiconductor memory chips;
- and
- a plurality of output signal lines coupled to the output buffers of each of said semiconductor memory chips;
- wherein each of said input switching circuits determines which one of the semiconductor memory chips should be selected, in accordance with said predetermined signals and a signal supplied through said M input signal lines.
3 more elements
A semiconductor memory system comprising:
- a system board having a plurality of inputs pins;
- and
- a plurality of semiconductor memory chips mounted on the system board, each of said semiconductor memory chips including a plurality of memory cells,
- wherein address signals are supplied to the input pins of the system board, the address signals having first address signals to designate the memory cells of semiconductor memory chips and second address signals to designate the semiconductor chips on the system board, the first address signals are divided into I groups, where I is an integer larger than 1, and supplied to the input pins in a divisional way I times, and the second address signals are included in at least one group of the I groups.
1 more element
A method for dividing address signals into K groups, where K is an integer larger than 1 , supplied to a system board in a divisional way K times, said system comprising a plurality of semiconductor memory chips each including a plurality of memory cells;
- and further comprising J input pins, where J is an integer larger than 1, said method comprising the steps of:
- supplying the dividing address signals divided by (K-n) groups, where n is a positive integer and smaller than K, to the input pins (K-n) times, the dividing address signals divided by (K-n) group include one part of address signals to designate the memory cells of the semiconductor memory chips, and supplying dividing address signals divided by n groups to the input pins n times, the dividing address signals divided by n groups include other part of address signals to designate the memory cells of semiconductor memory chips and address signals to designate the semiconductor chips on the system board.
Dependencies are inferred from the claim text.