Semiconductor integrated circuit and method of controlling same

Abstract

A semiconductor integrated circuit comprising: a pair of memory cores in which identical data are written; a refresh signal generating circuit; a refresh controlling circuit; and a read controlling circuit. The memory cores are operated during each predetermined period as refresh cores for performing a refresh operation and as read cores for performing a read operation. The refresh core performs refresh and write operations. The read core performs read and write operations. The write cycle time defined as an operation specification is set longer than the time necessary for each of the memory cores to perform a write operation. Therefore, during the refresh core, the time difference between the write cycle and the write operation is summed up during a plurality of write cycles to create a predetermined time margin. This time margin is utilized to perform a refresh operation so that the performance of the refresh operation, in conflict with the write operation, does not show to the exterior of the semiconductor integrated circuit. That is, even if a write operation is performed throughout the refresh core period, it is possible to prevent the data in the memory cores from being damaged. This enables users to use the semiconductor integrated circuit without taking refresh operations into consideration.

Dependencies are inferred from the claim text.