Reading device and method for integrated circuit memory
AssigneeSTMicroelectronics S.r.l.
InventorRichard Fournel
Life of this patent
Estimating the term…
Abstract
In a reading device for a memory, a circuit for the asymmetrical precharging of the differential amplifier is provided so that an output of the reading device switches over to a determined state. In the following evaluation phase, if the memory cell is programmed, the output remains unchanged. If the memory cell is blank or erased, the output of the reading device switches over to another state. A detection circuit detects a sufficient difference between the inputs of the differential amplifier for stopping the asymmetrical precharging and for making the reading device go automatically to the evaluation phase.
Claims35
A reading device for an integrated circuit memory comprising at least one memory cell to be read, at least one reference memory cell, a data bit line connected to the at least one memory cell and a reference bit line connected to the at least one reference memory cell, the reading device comprising:
- a data converter having an input connected to the data bit line;
- a reference converter having an input connected to the reference bit line;
- a differential amplifier having a data input connected to an output of said data converter for receiving a data signal therefrom, and a reference input connected to an output of said reference converter for receiving a reference signal therefrom;
- a read current generator connected to said differential amplifier for providing a reference current to the reference bit line and a fraction of the reference current to the data bit line;
- and
- an asymmetrical precharging circuit for causing the data signal being received at the data input of said differential amplifier to be at a level higher than the reference signal being received at the reference input of said differential amplifier for switching an output signal of said differential amplifier to a corresponding logic state.
A reading device for an integrated circuit memory comprising at least one memory cell to be read, at least one reference memory cell, a data bit line connected to the at least one memory cell and a reference bit line connected to the at least one reference memory cell, the reading device comprising:
- a differential amplifier having a data input for receiving a data signal, and a reference input for receiving a reference signal;
- a read current generator connected to said differential amplifier for providing a reference current to the reference bit line and a fraction of the reference current to the data bit line;
- and
- an asymmetrical precharging circuit for causing the data signal being received at the data input of said differential amplifier to be at a level higher than the reference signal being received at the reference input of said differential amplifier for switching an output signal of said differential amplifier to a corresponding logic state.
An integrated circuit memory comprising
- at least one memory cell to be read;
- a data bit line connected to said at least one memory cell;
- at least one reference memory cell;
- a reference bit line connected to said at least one reference memory cell;
- a reading device connected to said at least one memory cell and said at least one reference cell via said data and reference bit lines, said reading device comprising
- a data converter having an input connected to said data bit line,
- a reference converter having an input connected to said reference bit line,
- a differential amplifier having a data input connected to an output of said data converter for receiving a data signal therefrom, and a reference input connected to an output of said reference converter for receiving a reference signal therefrom,
- a read current generator connected to said differential amplifier for providing a reference current to said reference bit line and a fraction of the reference current to said data bit line, and
- an asymmetrical precharging circuit for causing the data signal being received at the data input of said differential amplifier to be at a level higher than the reference signal being received at the reference input of said differential amplifier for switching an output signal of said differential amplifier to a corresponding logic state.
Dependencies are inferred from the claim text.