Redundant row topology circuit, and memory device and test system using same

An integrated circuit, comprising:

• means for storing data including a primary storage means and a redundant storage means, each of the primary and redundant storage means storing data and having an associated data topology;
• means for transferring data between an external terminal and the means for storing data and for adjusting the data topology between data on the external terminal and data at the array responsive to a data topology signal;
• means for decoding an address responsive to a matching signal being inactive and for accessing corresponding data stored in the primary storage means, and for decoding an address responsive to the matching signal being active and for accessing corresponding data stored in the redundant storage means;
• means for storing a first and second state;
• and
• means for adjusting data topology responsive to the address having a value to apply an active matching signal to the means for decoding to access data stored in the redundant storage means, and for adjusting data topology responsive to the matching signal being active and the state of the means for storing the a first and second state to apply the data topology signal to the means for transferring data to adjust the data topology of the redundant storage means.

An integrated circuit including a memory storage circuit having a plurality of memory cells, the storage circuit including at least one redundant memory cell and each of the memory cells having an associated data topology, and the integrated circuit further including an address decoder adapted to receive an address and a matching signal, the address decoder operable when the matching signal is inactive to access a memory cell corresponding to the applied address, and operable when the matching signal is active to access a redundant memory cell, comprising:

• a data path circuit coupled between an external data terminal and the memory storage circuit, the data path circuit transferring data between the external terminal and data at the storage circuit being adjusted responsive to a data topology signal;
• a programmable data topology element having a first and second programmed states;
• and
• a data topology circuit coupled to the address decoder, data path circuit, and the programmable data topology element, the data topology circuit applying an active matching signal to the decoder to access a redundant memory cell in the storage circuit responsive to the address, and applying the data topology signal to the data path circuit to adjust the data topology of the accessed redundant memory cell responsive to the matching signal being active and the state of the programmable topology element.

A method for adjusting the data topology of redundant memory cells utilized to replace defective memory cells in an integrated circuit, each redundant memory cell having a corresponding data topology relative to the defective memory cell, comprising:

• identifying defective memory cells;
• replacing the defective memory cells with redundant memory cells;
• comparing the data topology of defective memory cells to the data topology of the redundant memory cells used to replace the defective memory cells;
• storing a topology bit in the memory device, the topology bit having a value that is a function of the result of comparing the data topology of the defective memory cells to the data topology of the redundant memory cells;
• and
• when data is to be transferred to the defective memory cells, adjusting the data topology of the redundant memory cell to match that of the replaced defective cell responsive to the topology bit.