US 6,324,104 B1Granted

Semiconductor integrated circuit device

AssigneeNEC Corporation

InventorYoshinori Matsui

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Abstract

A semiconductor integrated circuit device which can save defect bits in an auxiliary storage portion functioning as a cache memory is provided. A redundant SRAM cell array MAR is provided so as to be adjacent to a SRAM cell array MA of a SRAM portion functioning as a cache memory, and with the positions of rows matching. Redundant cells which are alternatively selected based on redundant selection signals, are arranged in matrix form in this redundant SRAM cell array MAR. Moreover, a data input/output line SIOR is provided in each row of this SRAM cell array MAR, and each data input/output line SIOR is connected to a global data input/output line GIOR via a data input/output line connection circuit which is alternatively conduction controlled based on a predetermined selection signal. This global data input/output line GIOR is connected to a read/write bus line together with a read/write amplifier which is used at normal times.

Claims6

Dependent claims

A semiconductor integrated circuit device having a main storage portion, and an auxiliary storage portion functioning as a cache memory, constructed such that two way data transfer is possible between said main storage portion and said auxiliary storage portion, said auxiliary storage portion comprising:

a normal memory cell array with memory cells which are alternatively selected based on a selection signal, arranged in matrix form, and
a redundant memory cell array provided so as to be adjacent to said memory cell array with the positions of rows matching, and with redundant memory cells which are alternatively selected based on a redundant selection signal, arranged in matrix form, wherein
a plurality of auxiliary data lines, to which memory cell groups of each row are connected, are separately provided for said normal memory cell array and for said redundant memory cell array,
wherein said semiconductor integrated circuit device comprises:
a data line connecting said main storage portion to said auxiliary storage portion,
a plurality of redundant auxiliary data lines provided along rows of said redundant memory cell array, to which redundant memory cell groups belonging to each row of said redundant memory cell array are connected, and
a plurality of redundant switch circuits respectively provided in said plurality of redundant auxiliary data lines, and alternatively conducting controlled based on a predetermined redundant address signal.

4 more elements

a memory cell array with memory cells which are alternatively selected based on a selection signal, arranged in matrix form;
a plurality of auxiliary data lines provided along rows of said memory cell array, to which memory cell groups belonging to each row of said memory cell array are connected;
a plurality of switch circuits respectively provided in said plurality of auxiliary data lines, and alternatively conducting controlled based on a predetermined address signal;
and
a main data line provided along columns of said memory cell array, and connected to said plurality of auxiliary data lines via said plurality of switching circuits;
wherein the semiconductor integrated circuit device comprises:
a redundant memory cell array provided so as to be adjacent to said memory cell array with the position of rows matching, and with redundant memory cells which are alternatively selected based on a redundant selection signal, arranged in matrix form,
and a plurality of redundant auxiliary data lines provided along rows of said redundant memory cell arrays, to which redundant memory cell groups belonging to each row of said redundant memory cell array are connected,
a plurality of redundant switch circuits respectively provided in said plurality of redundant auxiliary data lines, and alternatively conducting controlled based on a predetermined redundant address signal, and
a redundant main data line provided along columns of said redundant memory cell array, and connected to said plurality of redundant auxiliary data lines via said plurality of redundant switching circuits.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/519,073Filed 6 Mar 2000
Priority: JP 11-06409410 Mar 1999
Granted: 27 Nov 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 29/846
With improved access time or stability: by choosing redundant lines at an output stage
G06F 12/0893
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: caches…
G11C 14/00
Digital stores characterised by arrangements of cells having volatile and non-volatile storage
G06F 2212/3042
In main memory subsystem: being part of a memory device, e.g. cache DRAM