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US 6,324,098 B1Granted
Reading circuit for nonvolatile memory cells without limitation of the supply voltage
AssigneeSTMicroelectronics S.r.l.
InventorsCarmelo Condemi, Michele La Placa, Ignazio Martines
Life of this patent
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Abstract
A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.
Claims21
A reading circuit for nonvolatile memory cells, comprising:
- a current-to-voltage converter having an array load, connected to a memory cell, and a reference load connected to a reference generator;
- said array load having an array aspect ratio and said reference load having a reference aspect ratio;
- and the ratio between said array aspect ratio and said reference aspect ratio is a non-integer and the ratio between said reference aspect ratio and said array aspect ratio is also a non-integer.
A reading circuit, comprising:
- an array load transistor coupled to a memory cell transistor;
- a reference load transistor coupled to a reference generator comprising a first current mirror;
- and
- the array load transistor having an aspect ratio defined by (W/L)F and the reference load transistor having an aspect ratio defined by (W/L)R where W is defined as the width of the respective channel and L is defined as the length of the respective channel of the transistors, and the array load transistor and the reference load transistor are configured such that the ratio of (W/L)F to (W/L)R is a non-integer and the ratio of (W/L)R to (W/L)F is a non-integer.
1 more element
A reading circuit for nonvolatile memory cells, comprising:
- a first current mirror having an array branch connected to the memory cell and a reference branch connected to a reference circuit, the array branch having an array aspect ratio and the reference branch having a reference aspect ratio, and wherein the reference aspect ratio is greater than the array aspect ratio;
- and a charge pump coupled to a control gate of the memory cell, wherein the ratio between the array aspect ratio and the reference aspect ratio is a non-integer N/KB, wherein N represents the current amplification of the first current mirror, and KB represents the boosting efficiency of the charge pump.
A reading circuit for nonvolatile memory cells, comprising:
- a current-to-voltage converter having an array load connected to a memory cell and a reference load connected to a reference generator, the array loading having an array aspect ratio and the reference load having a reference aspect ratio, the ratio between the array aspect ratio and the reference aspect ratio is a non-integer;
- and
- boosting means supplying a biasing voltage to a gate terminal of the memory cell, the voltage being proportional to a supply voltage according to a multiplication factor greater than 1 and wherein the ratio is inversely proportional to the multiplication factor.
A reading circuit, comprising:
- an array load transistor coupled to a memory cell transistor;
- a reference load transistor coupled to a reference generator comprising a first current mirror, and coupled to the array load transistor to form a second current mirror;
- the array load transistor having an aspect ratio defined by (W/L)F and the reference load transistor having an aspect ratio defined by (W/L)R where W is defined as the width of the respective channel and L is defined as the length of the respective channel of the transistors, and the load transistor and the reference load transistor are configured such that the ratio of (W/L)F to (W/L)R is a non-integer;
- and
- a charge pump coupled to a control gate of the memory cell transistor, the array load transistor and the reference load transistor configured such that the ratio of the array load transistor aspect ratio to the reference load transistor aspect ratio is defined as (N/KB), where N is an integer representing the second current mirror amplification and KB represents a boosting efficiency of the charge pump.
2 more elements
A reading circuit, comprising:
- an array load transistor coupled to a memory cell transistor;
- a reference load transistor coupled to a reference generator comprising a first current mirror, and coupled to the array load transistor to form a second current mirror;
- the array load transistor having an aspect ratio defined by (W/L)F and the reference load transistor having an aspect ratio defined by (W/L)R where W is defined as the width of the respective channel and L is defined as the length of the respective channel of the transistors, and the load transistor and the reference load transistor are configured such that the ratio of (W/L)F to (W/L)R is a non-integer;
- and
- a charge pump coupled to a control gate of the memory cell transistor, the array load transistor and the reference load transistor configured such that the ratio of the array load transistor aspect ratio to the reference load transistor aspect ratio is defined as (N/KB), where N is an integer representing the second current mirror amplification and KB represents a boosting efficiency of the charge pump, wherein the charge pump provides a biasing voltage that is proportional to a supply voltage in accordance with a multiplication factor that is represented by the boosting efficiency of the charge pump KB that is greater than 1, and wherein the ratio (N/KB) is inversely proportional to the multiplication factor.
2 more elements
A reading circuit, comprising:
- an array load transistor coupled to a memory cell transistor;
- a reference load transistor coupled to a reference generator that comprises a current mirror;
- and
- the array load transistor having an aspect ratio defined by (W/L)F and the reference load transistor having an aspect ratio defined by (W/L)R where W is defined as the width of the respective channel and L is defined as the length of the respective channel of the transistors, and the array load transistor and the reference load transistor are configured such that the ratio of (W/L)F to (W/L)R is a non-integer, and the array load transistor is diode connected, and wherein the aspect ratio of the reference load transistor is N/KB times greater than the aspect ratio of the array load transistor, where N is an integer greater than unity and KB represents a multiplication factor greater than 1.
1 more element
A reading circuit for nonvolatile memory cells, comprising:
- a current-to-voltage converter having an array load connected to a memory cell and a reference load connected to a reference generator, the array load having an array aspect ratio and the reference load having a reference aspect ratio, and the ratio between the array aspect ratio and the reference aspect ratio is a non-integer, and the aspect ratio of the reference load is inversely proportionate to KB, where KB is a multiplication factor representing the ratio of a biasing voltage supplied to a gate terminal of the memory cell and a supply voltage.
Dependencies are inferred from the claim text.