256 meg dynamic random access memory

A dynamic random access memory, comprising:

• an array of memory cells, each comprised of two storage elements, said array of memory cells being organized into a plurality of array quadrants;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells, said plurality of peripheral devices includes an array I/O block for servicing each of said array quadrants, a plurality of data read multiplexers responsive to said array I/O blocks, a plurality of data output buffers responsive to said plurality of data read multiplexers, and a plurality of data pad drivers responsive to said plurality of data output buffers;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch circuit responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory elements, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory elements.

A dynamic random access memory, comprising:

• an array of memory cells, each comprised of two storage elements, said array of memory cells being organized into a plurality of array blocks;
• a power distribution bus including a first plurality of conductors forming a web around each of said array blocks and a second plurality of conductors extending from said web to form a grid within each of said array blocks;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices;
• a plurality of pads located centrally with respect to said array blocks, and wherein said power distribution bus includes a third plurality of conductors running parallel to said plurality of pads for receiving an external voltage from said plurality of pads and for distributing the external voltage to said plurality of voltage supplies;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch circuit responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory elements, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory elements.

A dynamic random access memory, comprising:

• an array of memory cells, each comprised of two storage elements;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch circuit responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory elements, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory elements, and
• wherein said array of memory cells is organized into a plurality of array blocks, and wherein said plurality of voltage supplies includes a voltage regulator comprised of a plurality of power amplifiers, and wherein at least one power amplifier is associated with each of said plurality of array blocks.

A dynamic random access memory, comprising:

• an array of memory cells, each comprised of two storage elements;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices, said plurality of voltage supplies includes a voltage pump including a plurality of voltage pump circuits divided into a plurality of groups for operation in one of separate and concurrent operation to achieve predetermined levels of output power;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch circuit responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory elements, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory elements.

A dynamic random access memory, comprising:

• an array of memory cells, each comprised of two storage elements;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch circuit responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory elements, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory elements, and
• wherein said array provides more than 256 meg of storage, said memory additionally comprising repair logic to logically replace defective memory cells with operable memory cells such that said memory provides said 256 meg of storage.

A system, comprising:

• a control unit for performing a series of instructions;
• and
• a dynamic random access memory responsive to said control unit, said memory comprising:
• an array of memory cells;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral device;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory cells, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory cells, wherein said test mode logic is responsive to an all row high test condition.

A system, comprising:

• a control unit for performing a series of instructions;
• and
• a dynamic random access memory responsive to said control unit, said memory comprising:
• an array of memory cells, said array being organized into rows and columns to form a plurality of individual arrays, and wherein said plurality of individual arrays is organized into a plurality of array blocks;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells, said plurality of peripheral devices includes a plurality of sense amplifiers positioned between adjacent rows of individual arrays and a plurality of row decoders positioned between adjacent columns of individual arrays, and wherein each of said plurality of individual arrays includes digitlines extending therethrough and into said sense amplifiers, and wherein said array blocks include I/O lines running between adjacent rows of individual arrays and through said sense amplifiers, said sense amplifiers including circuits for transferring signals on said digitlines to said I/O lines, said array blocks include datalines running between adjacent columns of individual arrays and through said row decoders to form intersections with said I/O lines, said plurality of peripheral devices including a plurality of multiplexers positioned at certain of said intersections of I/O lines and datalines for transferring signals on said I/O lines to said datalines;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory cells, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory cell.

A system, comprising:

• a control unit for performing a series of instructions;
• and
• a dynamic random access memory responsive to said control unit, said memory comprising:
• an array of memory cells, said array of memory cells being organized into a plurality of array quadrants;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells, said plurality of peripheral devices includes an array I/O block for servicing each of said array quadrants, a plurality of data read multiplexers responsive to said array I/O blocks, a plurality of data output buffers responsive to said plurality of data read multiplexers, and a plurality of data pad drivers responsive to said plurality of data output buffers;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral device;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory cells, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory cells.

A system, comprising:

• a control unit for performing a series of instructions;
• and
• a dynamic random access memory responsive to said control unit, said memory comprising:
• an array of memory cells;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral devices, said plurality of voltage supplies includes a voltage pump including a plurality of voltage pump circuits divided into a plurality of groups for operation in one of separate and concurrent operation to achieve predetermined levels of output power;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory cells, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory cell.

A system, comprising:

• a control unit for performing a series of instructions;
• and
• a dynamic random access memory responsive to said control unit, said memory comprising:
• an array of memory cells;
• a plurality of peripheral devices for writing data into said memory cells and for reading data out of said memory cells;
• a plurality of voltage supplies responsive to an external voltage for generating a plurality of supply voltages for use by said array and said plurality of peripheral device;
• and
• test mode logic for determining whether the memory is in a test mode, and wherein said plurality of peripheral devices includes a latch responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory cells, and a write enable circuit responsive to a second external signal when said memory is in the test mode, for enabling the latched data to be written to a second group of memory cells, and
• wherein said array provides more than 256 meg of storage, said memory additionally comprising repair logic to logically replace defective memory cells with operable memory cells such that said memory provides said 256 meg of storage.

A combination for use in a memory having an array of memory elements, said combination comprising:

• test mode logic for determining whether the memory is in a test mode;
• a latch responsive to a first external signal when the memory is in the test mode, for latching data stored in a first group of memory elements;
• and
• a write enable circuit responsive to a second external signal when the memory is in the test mode, for enabling the latched data to be written to a second group of memory elements, said write enable circuit being responsive to a plurality of changes in state of the second external signal for enabling the latched data to be written to a plurality of groups of memory elements, respectively.

A method of writing to a plurality of memory elements, comprising the steps of:

• writing known data into a first group of memory elements;
• latching the data from the first group of memory elements in response to a first external signal;
• writing the latched data into a second group of memory elements in response to a second external signal;
• and
• writing the latched data into another group of memory elements each time the second external signal changes states.

A method of testing a plurality of memory elements organized in a plurality of rows, comprising the steps of:

• writing test data into a first row of memory elements;
• latching the test data from the first row of memory elements in response to a first external signal;
• writing the latched test data into a first group of memory elements in response to a second external signal;
• writing the latched data into a second group of memory elements in response to a change in state of the second external signal;
• writing the latched data into a third group of memory elements in response to another change in state of the second external signal;
• writing the latched data into a fourth group of memory elements in response to a further change in state of the second external signal;
• reading the test data from the groups of memory elements;
• and
• comparing the test data read from the groups of memory elements with the test data written to the first row of memory elements.

A method of testing a portion of a memory array having a plurality of memory elements formed in a plurality of rows, and wherein said array is arranged in a plurality of memory blocks, said method comprising the steps of:

• selecting a memory block for testing;
• writing test data into a first row of memory elements in the selected memory block;
• latching the test data from the first row of memory elements in response to a first external row address strobe signal;
• writing the latched test data into a first plurality of rows of memory elements in response to a second external column address strobe signal;
• writing the latched data into another plurality of rows each time the column address strobe signal changes state;
• reading the test data from the pluralities of rows;
• and
• comparing the read test data with the test data written into the first row.

A method of inputting test mode information to a solid state device, comprising:

• inputting to the device a voltage outside the range of voltages used to represent logic signals;
• inhibiting the device from normal operation while said step of inputting a voltage is performed;
• enabling a detector;
• confirming the presence of the voltage outside the range of voltages used to represent logic signals;
• and
• inputting to the device at least one address containing test mode information.

A method of placing a solid state memory device into a test mode, comprising:

• applying to the device a voltage outside the range of voltages used to represent logic signals, and while said voltage is being applied;
• applying a specific combination of control signals to enable the receipt of a test enable key wherein the specific combination of control signals includes the assertion of the write signal followed by the assertion of the column address strobe and row address strobe signals;
• verifying the test enable key and confirming the presence of the applied voltage;
• applying said specific combination of control signals to enable the receipt of at least one test mode key;
• and
• decoding the test mode key to place the device in a test mode.

A solid state memory device, comprising:

• a plurality of memory cells;
• a plurality of peripheral devices for writing information into and reading information out of said memory cells;
• and
• a test logic circuit, comprising:
• a test mode enable circuit for determining if a voltage outside the range of voltages used to represent logic levels is being applied to the memory device under predetermined conditions, said test mode enable circuit includes logic for receiving a row address strobe signal (RAS), a write column address strobe before RAS signal, the applied voltage, and certain address information on column address lines and for producing therefrom a latch signal;
• a circuit for receiving and decoding test mode keys in response to said test mode enable circuit;
• a test mode reset circuit for resetting said circuit for receiving and decoding test mode keys, wherein said test mode reset circuit includes logic for receiving a row address strobe signal (RAS), a column address strobe signal (CAS), a write CAS before RAS signal and for producing therefrom a test mode reset signal and a super voltage test mode reset signal;
• and
• circuits, responsive to said decoded test mode keys, for performing tests on at least one of said memory cells and peripheral devices.