MISFET semiconductor device having relative impurity concentration levels between layers

A semiconductor device comprising a MISFET, said MISFET having:

• a first layer of semiconductor of a first conductivity type for forming a channel region;
• a gate electrode facing the channel region via a gate insulating film;
• a second layer of semiconductor of a second conductivity type formed in each of source and drain regions so as to be in contact with said first layer;
• a third layer formed on said second layer in each of the source and drain regions, said second layer being sandwiched between said first and third layers;
• and
• first and second main electrodes respectively connected to the source and drain regions,
• wherein an upper edge of said third layer is formed above a boundary between said first layer and said gate insulating film,
• in thermal equilibrium, a concentration of second conductivity type carriers in said third layer is lower than a concentration of second conductivity type carriers in said second layer, and is lower than a concentration of first conductivity type carriers in said first layer, and
• a sidewall insulating film is interposed between each of said source and drain regions and said gate electrode, and has an outer side surface inclined upward from said gate insulating film to said third semiconductor layer, such that said outer side surface is separated from said gate electrode more on an upper side, and said second and third semiconductor layers each have an end disposed on said outer side surface.

A semiconductor device having a MISFET, said MISFET comprising:

• a first semiconductor layer of a first conductivity type for forming a channel region;
• a gate electrode facing the channel region via a gate insulating film;
• a second semiconductor layer of a second conductivity type formed in each of source and drain regions so as to be in contact with said first semiconductor layer;
• a third semiconductor layer of the second conductivity type formed on said second semiconductor layer in each of the source and drain regions, said second semiconductor layer being sandwiched between said first and third semiconductor layers;
• and
• first and second main electrodes respectively connected to the source and drain regions,
• wherein an upper edge of said third semiconductor layer is formed above a boundary between said first semiconductor layer and said gate insulating film, and
• in thermal equilibrium, a concentration of second conductivity type carriers in said third layer is lower than a concentration of second conductivity type carriers in said second layer, and is lower than a concentration of first conductivity type carriers in said first layer, and
• a sidewall insulating film is interposed between each of said source and drain regions and said gate electrode, and has an outer side surface inclined upward from said gate insulating film to said third semiconductor layer, such that said outer side surface is separated from said gate electrode more on an upper side, and said second and third semiconductor layers each have an end disposed on said outer side surface,
• said gate electrode has a length of not more than 60 nm between said source and drain regions, and
• said second semiconductor layer of each of said source and drain regions terminates before said gate electrode in a direction so as to electrically connect said source and drain regions.