Method of supporting arrangement of semiconductor integrated circuit

A method for supporting the layout of semiconductor integrated circuits to determine the laid-out positions of logic blocks, by laying out logic blocks each comprising a plurality of logic elements on a layout drawing of a semiconductor integrated circuit board in an interactive mode, comprising the steps of:

• (a) providing in advance a logic block file comprising at least logic block names, logic block sizes and information on connection relationships with other logic blocks by extracting from a file of logic information;
• (b) preparing underlying information to provide the basis underlying the layout of a semiconductor integrated circuit chip;
• (c) displaying a list of logic block names extracted from said logic block file as a logic block name list in a logic block name window and underlying information in an underlying window on a display;
• (d) choosing the logic block name to be laid out from the logic block name window after activating the logic block name window;
• (e) executing the layout of said chosen logic block in the underlying window by designating a position for arrangement of said chosen logic block in accordance with the logic block scale of said logic block file after activating the underlying window;
• (f) repeating the steps (d) and (e) for other logic blocks to be laid out, if necessary;
• and
• (g) displaying the relationship of the laid-out logic block in the underlying window on the display according to its connection relationships with other logic blocks in said logic block file.