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AssigneeBull SAS
InventorsJean-François Autechaud, Christophe Dionet
Estimating the term…
The present invention relates to a process for detecting errors in an integrated circuit constituting a high-speed serial-parallel communication port and which allows a restart in case of an error, the port (100) comprising, in a sending part (40) which encodes each message, at last one buffer (TDBUF) for data to be transmitted issuing from a parallel bus and, in a receiving part (41), at least one buffer (RDBUF) for data to be received, the process comprising: checking the consistency of the messages, checking the consistency of a character stream constituting the messages, verifying the synchronous and cyclical utilization of the buffers of the sending (40) (TDBUF) and receiving (41) (RDBUF) parts, and checking the data of the messages by calculating a cyclic redundancy check (CRC) code on the data of each message.
A process for detecting errors in a high-speed serial-parallel communication port (100) between a parallel bus (L2CB, C2LB) and a serial link of an integrated circuit, the communication port (100) comprising a sending part (40) and a receiving part (41), the sending part having at least one buffer (TDBUF) for data to be transmitted issuing from the parallel bus, the receiving part (41) having at least one buffer (RDBUF) for data to be received, whereas the sending part (40) inserts each message or data set into a frame of control characters that convey information on the messages in question, and codes the characters of the messages at the bit level, and the receiving part (41) performs a complete verification of the messages before the message is written into the receiving buffer or buffers (RDBUF), characterized in that the buffers of the sending (40) and receiving (41) parts (TDBUF, RDBUF) of communication port (100) are equal in number and are used synchronously and cyclically, the process comprising:
A device for detecting errors in an integrated circuit for implementing an error detecting process in a high speed serial parallel communication port between a parallel bus (L2CB, C2LB) and a serial link, the integrated circuit comprising a serial link control function for constituting the high-speed serial-parallel communication port between the parallel bus (L2CB, C2LB) and the serial link, a port (100) including, in a sending part (40), at least one first buffer (TDBUF) for data of messages to be transmitted issuing from the parallel bus and means (109T) for serializing on output, and in a receiving part (41), at least one second buffer (RDBUF) for data of messages to be received and means (109R) for deserializing on input and means (106R) for checking the data of the messages by calculating a cyclic redundancy check code on all the data of each message to be transmitted, characterized in that the sending part (40) comprises means for inserting each message or data set into a frame of control characters that convey information on the messages in question, and means (108T) for coding the characters, the receiving part (41) comprising means for isolating the characters of the messages by separating the messages from the control characters and means (1023R) for the complete verification of the messages before the latter are written into the receiving buffer or buffers (RDBUF), the sending (40) and receiving (41) parts having the same number of buffers, operating synchronously and cyclically, the device further comprising means (1023R) for on-the-fly consistency checking of the messages at the level of coding of the messages into bits, means (1023R) for on-the-fly consistency checking of the character stream constituting the messages and means (1023R) for on-the-fly checking that the first and the second buffers of the sending (40) (TDBUF) and receiving (41) (RDBUF) parts are operating synchronously and cyclically.
Dependencies are inferred from the claim text.