System including a ferroelectric memory
AssigneeHitachi, Ltd.
InventorsKan Takeuchi, Hiroyuki Tanikawa
Life of this patent
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Abstract
A system with a ferroelectric memory has a low probability of soft error thereby decreasing the possibility of serious damage to the system that might result from soft errors. The ferroelectric memory is provided with an overwrite-inhibited memory block 122 for storing this OS (Operating System) and applications, and an overwrite-free memory block 123 which is a work area. The overwrite-inhibited memory block 122 includes a parity bit storage 125. A process for checking and correcting error performed about one a day. A command for starting the error checking and correcting procedures is triggered by a switch such as power source switch. When an error occurs in the ferroelectric memory 120, it is possible to recover the function of the system.
Claims14
A system comprising:
- a first memory block including a plurality of memory cells, each having a ferroelectric capacitor and a field-effect transistor;
- and
- a CPU coupled to said first memory block,
- wherein said first memory block having a first area for storing ordinary data and a second area for storing additional data for error correction of the ordinary data,
- wherein said system has a first mode and a second mode,
- wherein in the first mode, said CPU accesses the ordinary data without performing an error-checking and correction procedure for the ordinary data using the additional data and a write ordinary to said first memory block is inhibited, and
- wherein in said second mode, a write operation to said first memory block is allowed and said system performs a procedure having an error-checking for the ordinary data using the additional data and a writing back a corrected data into the first memory block when an error is detected by the error-checking.
A semiconductor device having a first mode and a second mode comprising:
- a first memory block including a plurality of memory cells, each cell having a ferroelectric capacitor and a field-effect transistor;
- a first control circuit for setting said first memory block to an overwrite-inhibited state;
- and
- a second control circuit for generating a signal indicating an overwrite-free state of said first memory block and for automatically returning the first memory block to the overwrite-inhibited state from the overwrite-free state in the second mode,
- wherein data is enabled to be written into said first memory block in the overwrite-free state in the second mode.
Dependencies are inferred from the claim text.