Semiconductor integrated circuit and method of testing the same

An LSI having a logic circuit and a test circuit incorporated therein, comprising:

• a first register connected between an LSI input/output pin and said logic circuit for receiving an input signal from said LSI input/output pin and outputting said input signal in accordance with a system clock signal;
• a selector circuit connected to said first register and said LSI input/output pin for selecting any one of an output of said first register and said input signal in accordance with a signal indicative of a test item for the LSI;
• a second register connected to an output of said selector circuit for providing the output from said selector circuit in accordance with another clock signal;
• and
• a third register connected to said second register for receiving an output of said second register and providing the output from said second register in accordance with a further clock signal;
• wherein said first register receives the output of said second register and selectively provides any one of the output of said second register and the input signal to said logic circuit in accordance with said system clock signal and a still further clock.

An LSI having a logic circuit and a test circuit, comprising:

• a first register connected between said logic circuit and an LSI input/output pin, and coupled to receive input signals and to provide an output in accordance with a clock signal;
• a second register coupled to receive an output of said first register and scan-in data, and to provide an output which serves as one of the input signals to said first register;
• a third register coupled to receive an output of said second register and to provide the output from said second register as scan-out data in accordance with another clock signal;
• and
• a selector circuit connected to said first register and arranged to select one of a signal relating to the scan-out data and an output of said second register so that the selected signal is inputted to said first register.

A signal processing method in a boundary scan circuit having a plurality of flip-flops including a user register having two inputs, a master register having two inputs and a slave register having an input disposed between a user's logic and an LSI input/output pin in an LSI circuit, said method comprising:

• inputting a data signal for said user's logic and a system clock signal to one of said two inputs of said user register which provides a signal to said user's logic;
• receiving a scan data signal from an output of said master register and a scan clock signal to the other of said two inputs of said user register and to said input of said slave register at the time of boundary scan;
• selecting LSI scan-in data by inputting an LSI internal test mode signal to one of said two inputs of said master register at the time of a LSI internal test mode;
• and
• inputting said LSI scan-in data inputted from said LSI input/output pin to the other of said two inputs of said master register.

A signal processing method in a boundary scan circuit including a plurality of flip-flops disposed between a user's logic and an LSI pin in an LSI circuit, said boundary scan circuit including a master register having two inputs, a slave register connected to said master register and having an input, and a user register having two inputs at a stage in rear of said master register, said method comprising:

• inputting a data signal for said user's logic and a system clock signal to one of said two inputs of said user register which provides a signal to said LSI pin;
• inputting a scan data signal and a scan clock signal to the other one of said two inputs of said user register;
• selecting an output of said master register at the time of boundary scan, and LSI scan-out data at the time of LSI scan-out for input to said other one of said two inputs of said user register in accordance with an LSI internal test mode signal;
• and
• inputting an output of said master register to the input of said slave register.

A boundary scan circuit arranged to conduct a sequence of testing operations for faulty connections of an integrated circuit (IC), said boundary scan circuit comprising:

• a first register connected between a signal input/output (I/O) pin and said integrated circuit (IC), and having input terminals coupled to receive input signals and a first clock signal, and an output terminal arranged to provide an output signal in accordance with said first clock signal;
• a second register having input terminals coupled to receive scan-in data, the output signal from said first register and a second clock signal, and an output terminal arranged to provide an output signal in accordance with said second clock signal which serves as one of the input signals of said first register;
• a third register having input terminals coupled to receive the output signal from said second register and a third clock signal, and an output terminal arranged to provide scan-out data;
• and
• a selector arranged to control operation of one of said first register and said second register, in dependence upon whether said signal I/O pin serves as an input pin for supplying another one of the input signals of said first register to said first register or an output pin for supplying the output signal of said first register to said integrated circuit (IC), so as to conduct said sequence of testing operations for faulty connections of said integrated circuit (IC).