Integrated circuit tester having a disk drive per channel

Abstract

An integrated circuit (IC) tester includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. Each tester channel includes a disk for storing several instruction sets, each including instructions and control data defining a separate test. To set up the tester for a test, a host computer sends a command to each channel identifying the instruction set to be used. Each channel then executes the instructions of the identified set during the test. Each channel also includes a high-speed instruction memory that can read out instructions at a higher rate than the disk. Before starting a test, each channel moves instructions covering high-speed portions of the test from the disk to the instruction memory. Thereafter, during those high-speed portions of the test in which instructions must be read out and executed at a high rate, each channel acquires those instructions from its instruction memory. During low-speed portions of the test, each channel acquires instructions to be executed directly from the disk.

Dependencies are inferred from the claim text.