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US 6,321,343 B1Granted
Semiconductor memory system comprising synchronous DRAM and controller thereof
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
Estimating the term…
Abstract
A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.
Claims50
A semiconductor device comprising:
- a delay circuit through which a reference signal passes;
- a reception circuit for receiving a plurality of control signals, the plurality of control signals being generated from a plurality of address areas of a plurality of external units;
- and
- a register circuit for storing a duration during which the reference signal passes through the delay circuit, the duration being determined in response to the plurality of control signals received by the reception circuit,
- wherein the register circuit is overwritten by the duration during which the reference signal passes through the delay circuit for each of the plurality of control signals and holds a largest amount of delay of the plurality of control signals from the reference signal.
2 more elements
A semiconductor device comprising:
- a reference signal output circuit for outputting a reference signal to a plurality of external units having a plurality of address areas;
- a reception circuit for receiving a plurality of control signals, the plurality of control signals being generated from the plurality of address areas of the plurality of external units in response to the reference signal;
- a delay circuit through which the reference signal passes;
- and
- a register circuit for storing a duration during which the reference signal passes through the delay circuit, the duration being determined in response to the plurality of control signals received by the reception circuit,
- wherein the register circuit is overwritten by the duration during which the reference signal passes through the delay circuit for each of the plurality of control signals and holds a largest amount of delay of the plurality of control signals from the reference signal.
3 more elements
A semiconductor device comprising:
- a delay circuit through which a reference signal passes;
- a reception circuit for receiving a plurality of control signals, the plurality of control signals being generated from a plurality of address areas of a plurality of external units;
- and
- a register circuit for holding a duration during which the reference signal passes through the delay circuit, based on one of the plurality of control signals received by the reception circuit, which has a largest amount of delay from the reference signal.
1 more element
A semiconductor device comprising:
- a reference signal output circuit for outputting a reference signal to a plurality of external units having a plurality of address areas;
- a reception circuit for receiving a plurality of control signals, the plurality of control signals being generated from the plurality of address areas of the plurality of external units in response to the reference signal;
- a delay circuit through which the reference signal passes;
- and
- a register circuit for holding a duration during which the reference signal passes through the delay circuit, based on one of the plurality of control signals received by the reception circuit, which has a largest amount of delay from the reference signal.
2 more elements
A method for measuring a maximum delay time, comprising:
- receiving a first control signal generated from a first address area of a plurality of external units;
- causing a duration during which a reference signal passes through a delay circuit to be stored in a register circuit in response to the first control signal;
- receiving a second control signal generated from a second address area of the plurality of external units;
- and
- overwriting the register circuit by the duration during which the reference signal passes through the delay circuit, in response to the second control signal.
2 more elements
A method for measuring a maximum delay time, comprising:
- outputting a reference signal from a reference signal output circuit to a first address area of a plurality of external units;
- receiving a first control signal generated from the first address area of the plurality of external units in response to the reference signal;
- causing a duration during which the reference signal passes through a delay circuit to be stored in the register circuit in response to the first control signal;
- outputting the reference signal from the reference signal output circuit to a second address area of the plurality of external units;
- receiving a second control signal generated from the second address area of the plurality of external units in response to the reference signal;
- and
- overwriting the register circuit by the duration during which the reference signal passes through a delay circuit in response to the second control signal.
4 more elements
A semiconductor device, comprising:
- a reference signal output circuit that generates a reference signal;
- a plurality of external units having a plurality of address areas that hold data to be read, wherein each of the plurality of address areas generate a control signal output with the data in response to the reference signal;
- a reception circuit that receives each of the plurality of control signals;
- a delay circuit, wherein the reference signal passes through the delay circuit each time one of the plurality of control signals is received by the reception circuit;
- a register circuit adapted to store a duration of a delay of each of the plurality of control signals from the reference signal each time one of the plurality of control signals is received by the reception circuit, wherein the register circuit is adapted to be overwritten by the duration of one of the plurality of control signals having a largest amount of delay from the reference signal, and adapted to hold the duration of one of the plurality of control signals having the largest amount of delay from the reference signal;
- and
- a timing signal generation circuit for generating timing signals for capturing data from the plurality of external units by delaying the reference signal by the largest amount of delay.
4 more elements
Dependencies are inferred from the claim text.