Method and apparatus for interfacing circuits that operate based upon different clock signals

A method of interfacing a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal with a third circuit, comprising the steps of:

• a) applying said first clock signal and said second clock signal to a clock selector for said third circuit;
• b) transferring first data signals between said third circuit and said first circuit at a first rate based upon said first clock signal;
• c) causing said clock selector to apply said first clock signal to said third circuit prior to step (b);
• d) transferring second data signals between said third circuit and said second circuit at a second rate based upon said second clock signal;
• and
• e) causing said clock selector to apply said second clock signal to said third circuit prior to step (d).

A system, comprising:

• a first clock source operable to generate a first clock signal;
• a second clock source operable to generate a second clock signal;
• a first circuit coupled to said first clock source in order to receive said first clock signal, said first circuit configured to operate at a first rate based upon said first clock signal;
• a second circuit coupled to said second clock source in order to receive said second clock signal, said second circuit configured to operate at a second rate that is based upon said second clock signal;
• a third circuit coupled to said first circuit and said second circuit, said third circuit configured to (i) operate at said first rate in response to receiving said first clock signal, and (ii) operate at said second rata in response to receiving said second clock signal;
• a clock selector coupled to (i) said first clock source in order to receive said first clock signal, and (ii) said second clock source in order to receive said second clock signal, said clock selector operable to (i) apply said first clock signal to said third circuit in response to first control signals in order to cause said third circuit to operate at said first rate, and (ii) apply said second clock signal to said third circuit in response to second control signals in order to cause said third circuit to operate at said second rate;
• and
• a clock selector control coupled to said clock selector, said clock selector control operable to (i) generate said first control signals prior to a first data transfer between said third circuit and said first circuit, and (ii) generate said second control signals prior to a second data transfer between said third circuit and said second circuit.