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US 6,321,324 B1Granted
Device for putting an integrated circuit into operation
AssigneeSGS-Thomson Microelectronics S.A.
InventorMaurice Le Van Suu
Life of this patent
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Abstract
To enable the putting into use of a monolithic integrated circuit comprising a processor and a fuzzy logic coprocessor, both having a single program memory in common, an operation is effected by which, at the time of the initializing of the integrated circuit, a volatile, random-access memory of the coprocessor is loaded with instructions stored in this single program memory.
Claims28
A device for putting into operation an integrated circuit that comprises a program memory, a first logic processor and a fuzzy logic coprocessor, said device comprising:
- a volatile random-access memory linked with the coprocessor to store rules for the fuzzy logic coprocessor, and
- a loading circuit for loading of the volatile random-access memory, the loading circuit comprising means to prompt loading when the integrated circuit is put into operation;
- wherein the program memory comprises at least one duplicated part and, in an associated decoder, an additional decoding access to decode a signal produced by a counter in order to access the duplicated part of the program memory;
- wherein said loading circuit includes at least one of, a) means for loading the random-access memory from the contents of the program memory;
- and b) means for loading the random-access memory from an input/output circuit.
2 more elements
A device for putting into operation an integrated circuit that comprises a program memory, a first logic processor and a fuzzy logic coprocessor, said device comprising:
- a volatile random-access memory linked with the coprocessor to store rules for the fuzzy logic coprocessor, and
- a loading circuit for loading of the volatile random-access memory, the loading circuit comprising means to prompt loading when the integrated circuit is put into operation;
- wherein the program memory comprises at least one duplicated part and, in an associated decoder, an additional decoding access to decode a signal produced by a counter in order to access the duplicated part of the program memory;
- wherein said loading circuit includes at least one of, a) means for loading the random-access memory from the contents of the program memory;
- and b) means for loading the random-access memory from an input/output circuit;
- wherein the loading circuit comprises a forward-backward counter controlled by a clock to produce addresses, in the program memory of the integrated circuit, of memory words of the program memory to be loaded into the random-access memory of the coprocessor;
- wherein the forward-backward counter comprises means to be configured with an initial value, at the time when the integrated circuit is put into use, before performing a countdown operation.
4 more elements
A device for putting into operation an integrated circuit that comprises a program memory, a first logic processor and a fuzzy logic coprocessor, the device comprising:
- a volatile random-access memory linked with the fuzzy logic coprocessor to store rules for the fuzzy logic coprocessor;
- a loading circuit for loading of the random-access memory, the loading circuit comprising means to prompt loading when the integrated circuit is put into operation, and
- an address bus for connection of the program memory to the logic processor, the loading circuit comprising a multiplexer having a first input connected to the address bus, and a second input receiving addressing signals produced in this loading circuit.
A device for putting into operation an integrated circuit that comprises a program memory, a first logic processor and a fuzzy logic coprocessor, the device comprising:
- a volatile random-access memory linked with the fuzzy logic coprocessor to store rules for the fuzzy logic coprocessor;
- a loading circuit for loading of the random-access memory, the loading circuit comprising means to prompt loading when the integrated circuit is put into operation, and
- an address bus for connection of the program memory to the logic processor, the loading circuit comprising a multiplexer having a first input connected to the address bus, and a second input receiving addressing signals produced in this loading circuit;
- wherein the loading circuit comprises a forward-backward counter controlled by a clock to produce addresses, in the program memory of the integrated circuit, of memory words of the program memory to be loaded into the random-access memory of the coprocessor;
- wherein the forward-backward counter comprises means to be configured with an initial value, at the time when the integrated circuit is put into use, before performing a countdown operation.
2 more elements
A circuit for operating an integrated circuit comprising:
- a microprocessor;
- a fuzzy logic microprocessor;
- a program memory associated with the microprocessor;
- a random-access memory associated with the fuzzy logic microprocessor for storing rules for use by the fuzzy logic microprocessor;
- an address bus for interconnection of the program memory, microprocessor, and random-access memory;
- a loading circuit comprising means for only initiating loading of the random-access memory when the integrated circuit is put into operation.
3 more elements
A circuit for operating an integrated circuit comprising:
- a microprocessor;
- a fuzzy logic microprocessor;
- a program memory associated with the microprocessor;
- a random-access memory associated with the fuzzy logic microprocessor for storing rules for use by the fuzzy logic microprocessor;
- an address bus for interconnection of the program memory, microprocessor, and random-access memory;
- a loading circuit comprising means for only initiating loading of the random-access memory when the integrated circuit is put into operation;
- including a decoder associated with the program memory also receiving the address bus;
- including a data bus, said microprocessor, said program memory and said random access memory all being connected to said data bus;
- wherein the rules to be loaded into said random-access memory are able to be communicated, under control of said loading circuit, from said program memory to said random-access memory over said data bus;
- wherein said program memory comprises at least one duplicated part;
- wherein said loading circuit comprises a counter for providing an addressing signal for coupling to said decoder;
- wherein said counter comprises a bi-directional counter controlled by a clock to produce the addressing signals of the program memory to be loaded in the random-access memory;
- wherein the counter includes means to be configured with an initial value, at the time when the integrated circuit is put into use, before performing a countdown operation;
- wherein the means to be configured comprise a power-on-reset circuit.
11 more elements
A circuit for operating an integrated circuit comprising:
- a microprocessor;
- a fuzzy logic microprocessor;
- a program memory associated with the microprocessor;
- a random-access memory associated with the fuzzy logic microprocessor for storing rules for use by the fuzzy logic microprocessor;
- an address bus for interconnection of the program memory, microprocessor, and random-access memory;
- a loading circuit comprising means for only initiating loading of the random-access memory when the integrated circuit is put into operation;
- including a decoder associated with the program memory also receiving the address bus;
- including a data bus, said microprocessor, said program memory and said random access memory all being connected to said data bus;
- wherein the rules to be loaded into said random-access memory are able to be communicated, under control of said loading circuit, from said program memory to said random-access memory over said data bus;
- wherein said loading circuit comprises a counter for providing an addressing signal for coupling to said decoder;
- wherein the counter includes means to be configured with an initial value, at the time when the integrated circuit is put into use, before performing a countdown operation;
- and
- wherein the means to be configured comprise a power-on-reset circuit.
10 more elements
A circuit for operating an integrated circuit comprising:
- a microprocessor;
- a fuzzy logic microprocessor;
- a program memory associated with the microprocessor;
- a random-access memory associated with the fuzzy logic microprocessor for storing rules for use by the fuzzy logic microprocessor;
- an address bus for interconnection of the program memory, microprocessor, and random-access memory;
- a loading circuit comprising means for only initiating loading of the random-access memory when the integrated circuit is put into operation.
- including a decoder associated with the program memory also receiving the address bus;
- including a data bus, said microprocessor, said program memory and said random-access memory all being connected to said data bus;
- wherein the rules to be loaded into said random-access memory are able to be communicated, under control of said loading circuit, from said program memory to said random-access memory over said data bus;
- wherein said loading circuit comprises a counter for providing an addressing signal for coupling to said decoder;
- and
- including a multiplexer having a first input connected to the address bus and a second input receiving the counter addressing signals.
9 more elements
Dependencies are inferred from the claim text.