Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

An instruction architecture comprising:

• an n-bit instruction, wherein n=m×16 with m being an integer greater than or equal to one;
• an m-bit hierarchical bit field within the n-bit instruction defining at least one instruction type of the n-bit instruction for instruction decode and execution;
• and
• an (n−m)-bit field within the n-bit instruction for actual instruction bits;
• wherein m=1 and the 1 bit hierarchical bit filed indicates a distinction between two types of instructions, a first instruction type which includes indirect very long instruction word and control instructions, and a second instruction type which includes arithmetic and load/store instructions.

An instruction architecture comprising:

• an n-bit instruction, wherein n=m×16 with m being an integer greater than or equal to one;
• an m-bit hierarchical bit field within the n-bit instruction defining at least one instruction type of the n-bit instruction for instruction decode and execution;
• and
• an (n−m)-bit field within the n-bit instruction for actual instruction bits;
• wherein m=2 and the 2-bit hierarchical bit field indicate a distinction between a first group of instructions and a second group of three major types of instructions;
• wherein a first major type of instruction for said second group comprises indirect very long instruction word and control opcodes.

A SIMD machine with an array comprising at least one processing element (PE) and an array control processor, the array control processor comprising:

• a scalable hierarchical instruction set memory;
• and
• a plurality of instructions comprising the scalable hierarchical instruction set, at least one instruction including a hierarchical bit field which defines an instruction type for instruction decode and execution;
• wherein the plurality of instructions can execute on both the array control processor and the at least one PE when the instructions are fetched by the control processor.