Set-associative cache-management method with parallel and single-set sequential reads
AssigneeVLSI Technology, Inc.
InventorMark W. Johnson
Life of this patent
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AssigneeVLSI Technology, Inc.
InventorMark W. Johnson
Estimating the term…
A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.) However, the invention further provides for comparing the tag at the same-set location with the successor index with the tag associated with a location from which a read request was satisfied. If the next read request matches the common tag and the index of the successor location, a single-set read is also used. The single-set reads save power relative to the parallel reads, while maintaining the speed advantages of the parallel reads over serial “tag-then-data” reads.
A cache-management method for a computer system having a processor that indicates whether a read request is sequential or non-sequential, said method comprising the steps of:
Dependencies are inferred from the claim text.