User-configurable on-chip program memory system

A microprocessor comprising:

• a central processing unit;
• an on-chip memory array for storing instructions executable on said central processing unit;
• an external memory interface capable of reading from and writing to an off-chip memory instructions executable on said central processing unit;
• and
• a configurable program memory controller in communication with said central processing unit, said on-chip memory array, and said external memory interface, said configurable program memory controller having a plurality of operating modes, including a first mode in which it uses said on-chip memory array as a memory-mapped on-chip memory, and a second mode in which it uses said on-chip memory array as a cache on-chip memory, said configurable program memory controller operable to always load said on-chip memory from predetermined locations of off-chip memory via said external memory interface upon each and every transition between said second mode to said first mode.

A method of operating a microprocessor having a central processing unit, an on-chip memory operable in a first mode and a second mode and an external memory interface capable of reading from and writing to off-chip memory, the method comprising the steps of:

• operating said on-chip memory as a memory-mapped memory having a predetermined range of addresses when in said first mode;
• operating said on-chip memory as a cache memory when in said second mode;
• and
• transiting from said second mode to said first mode only following a cache miss.

A method of operating a microprocessor having a central processing unit, an on-chip memory operable in a first mode and a second mode and an external memory interface capable of reading from and writing to off-chip memory, the method comprising the steps of:

• operating said on-chip memory as a memory-mapped memory having a predetermined range of addresses when in said first mode;
• operating said on-chip memory as a cache memory when in said second mode;
• and
• always loading said on-chip memory from predetermined locations of said off-chip memory via said external memory interface upon transiting from said second mode to said first mode.