Method and apparatus for local control signal generation in a memory device
AssigneeMicron Technology, Inc.
InventorTroy A. Manning
Life of this patent
Estimating the term…
Abstract
A computer system with a memory device having plural memory banks and a method of accessing a selected one of the memory banks, the memory device includes local control signal generators that control timing of operations in each respective block of a memory array. Overall timing of the device is controlled by first and second global control signals generated in a command sequencer and decoder. The second global control signal is derived from a delayed version of the first signal, and both signals are applied to local control signal generators along with address bits indicating a selected block. Local timing is determined by the global control signals and by local circuitry within the local control signal generators.
Claims31
A method of transferring data to or from a memory device having a plurality of physically spaced-apart memory banks each of which corresponds to a respective bank address, the method comprising:
- receiving a command signal;
- receiving a bank address;
- generating one of a plurality of global control signals responsive to the command signal and the bank address;
- coupling the generated global control signal to the memory bank corresponding to the received address;
- receiving the global control signal at the memory bank corresponding to the received address;
- generating a plurality of local control signals at the memory bank corresponding to the received address responsive to the received global control signal, the local control signals having predetermined timing relationships;
- coupling the local control signals to the memory bank corresponding to the received address,
- transferring data to or from the memory bank corresponding to the bank address in response to the local control signals.
A method of accessing a memory array including a plurality of memory banks, comprising:
- receiving a command signal;
- receiving a bank address;
- producing a first global control signal including a first transition in response to the command signals and producing a second global control signal from the first global control signal;
- directing the first and second global control signals to one of a plurality of local control circuits located proximate and coupled to a memory bank corresponding to the received bank address;
- and
- generating a first set and a second set of local control signals at the local control circuit responsive to receipt of the first and second global control signals, the first and second local control signals causing an access to the memory bank to which the local control circuit is coupled.
A method of accessing a selected one of a plurality of memory banks in a memory device responsive to an address, including a bank address, comprising:
- coupling respective local control circuits to each of the memory banks, the local control circuits being located proximate the respective memory banks;
- receiving a bank address indicating one of the local control circuits;
- coupling the indicated one of the local control circuits to a global control circuit;
- generating a global signal at the global control circuit;
- at the indicated local control circuit, generating a plurality of local control signals in response to the global signal;
- and
- reading data from or writing data to the bank to which the indicated local control circuit is coupled responsive to the local control signals.
A memory device comprising:
- a memory array having a plurality of physically separated memory banks;
- a global control circuit configured to produce a global control signal;
- a plurality of local control circuits, each being physically proximate and coupled to a respective one of the memory banks, each of the local control circuits being operable to activate a selected row of the respective memory bank in response to receiving the global control signal;
- and
- a bank selector circuit coupled between the global control circuit and each of the local control circuits through a respective global signal line extending between the bank selector circuit and each of the local control circuits, the bank selector circuit being operable to couple the global control signal to a local control circuit designated by a bank address.
A computer system comprising:
- a processor;
- an input device coupled to the processor;
- an output device coupled to the processor;
- a data storage device coupled to the processor;
- and
- a memory device coupled to the processor, the memory device comprising:
- a memory array having a plurality of physically separated memory banks;
- a global circuit configured to produce a global control signal;
- a plurality of local control circuits, each being physically proximate and coupled to a respective one of the memory banks, each of the local control circuits being operable to activate a selected row of the respective memory bank in response to receiving the global control signal;
- and
- a bank selector circuit coupled between the global control circuit and each of the local control circuits through a respective global signal line extending between the bank selector circuit and each of the local control circuits, the bank selector circuit being operable to couple the global control signal to a local control circuit designated by a bank address.
Dependencies are inferred from the claim text.