Method and apparatus to reduce memory read latency
AssigneeMicron Technology, Inc.
InventorPaul A. LaBerge
Life of this patent
Estimating the term…
Abstract
A memory controller to reduce the latency associated with multi-quanta system memory read operations is described. The memory controller transfers a first quantum of data (e.g., 64-bits or 32-bits) toward a requesting device upon its receipt from system memory. Subsequent data quanta may be aggregated to more fully utilize intra-memory controller data transfer pathways (e.g., 256-bits or 128-bits). Because intra-memory controller data pathways are wider than external data transfer pathways (e.g., memory bus and processor bus data paths), an indication of which portion or portions of the transferred data is valid is forwarded with the data.
Claims27
A memory transfer method, comprising:
- receiving a first quantum of data having a width from a memory device;
- transferring the first quantum of data to a device on a first clock;
- receiving a second and third quanta of data from the memory device, each of the second and third quanta having the width;
- concurrently transferring both the second and third quanta of data to the device on a successive clock.
A data transfer apparatus, comprising:
- a receiver means for receiving a first quantum of data from a memory device, the first quantum of data having a width;
- a transfer means for transferring the first quantum of data to a device on a first clock signal;
- a second receiver means for receiving a second and third quantum of data from a memory, each of said second and third quantum of data having the width;
- and
- a second transfer means for concurrently transferring both the second and third quantum of data to the device on a next clock signal.
A data transfer apparatus, comprising:
- a receiver to receive a first quantum of data from a memory device, the first quantum of data having a width;
- a transfer circuit to transfer the first quantum of data to a device on a first clock signal;
- a second receiver to receive a second and third quantum of data from a memory, each of said second and third quantum of data having the width;
- and
- a second transfer circuit to concurrently transfer both the second and third quantum of data to the device on a next clock signal.
Dependencies are inferred from the claim text.