System and method for controlling peripheral device memory access in a data processing system
AssigneeInternational Business Machines Corporation
InventorsGordon Taylor Davis, Llewellyn Bradley Marshall, IV, Clarence Rosser Ogilvie, Paul Colvin Stabler
Life of this patent
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Abstract
A cache based processing system is provided with a loop detection circuit for detecting the entry into and termination of program loops and for enabling peripheral device access to the main memory after completion of the first pass through the loop and terminating access when the program leaves the loop.
Claims8
A method for controlling data transfers between a peripheral device and a random access memory in a cache-based processor system comprising the steps:
- detecting when a program executing in the processor has entered a processing loop and has completed at least one pass through the processing loop;
- at the completion of the at least one pass through the processing loop authorizing access to random access memory by the peripheral device;
- monitoring the operation of the program to detect termination of loop processing;
- and,
- terminating access authorization to the random access memory previously granted to the peripheral device when loop termination is detected.
A system for controlling data transfers between a peripheral device and a random access memory in a cache-based processor system comprising:
- first means for detecting when a program executing in the processor has entered a processing loop and has completed at least one pass through the processing loop;
- second means responsive to the first means for providing memory access authorization signals to the peripheral device at the completion of the at least one pass through the processing loop;
- and,
- third means for monitoring the operation of the program to detect termination of loop processing and providing a signal to the second means for terminating the authorization signals.
A system for controlling data transfers between a peripheral device and a random access memory in a cache-based processor system comprising:
- first means for detecting when a program executing in the processor has entered a processing loop having a plurality of sequential instruction addressed appearing in an instruction address bus and has completed at least one pass through the processing loop;
- second means responsive to the first means for providing memory access authorization signals to the peripheral device at the completion of the at least one pass through the processing loop;
- and,
- third means for monitoring the operation of the program to detect termination of loop processing and providing a signal to the second means for terminating the authorization signals.
A method for controlling data transfers between a peripheral device and a random access memory in a cache-based processor system equiped with loop control hardware providing top of loop (TOL), last instruction address (LIA) and loop count (LC) signals comprising the steps:
- comparing the current instruction address from the processor to the last instruction address (LIA);
- at equality, decrementing the loop count (LC) by one, initiate authorization of data transfers between a peripheral device and the random access memory if the loop count (LC) is not zero and forcing a branch on the next instruction;
- and,
- repeating the above steps until the loop count (LC) reaches zero at which time terminating authorization of data transfers between the peripheral device and random access memory.
Dependencies are inferred from the claim text.