Interleave read address generator
AssigneeSamsung Electronics Co., Ltd.
InventorDae-Jung Kim
Life of this patent
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Abstract
An interleave read address generator of an interleaver for use in a CDMA mobile communication terminal. The interleave read address generator includes a base-18 counter for counting a clock input on a base 18, to generate column address bits, a base-32 counter being enabled in response to a carry output from base-18 counter, for counting the clock input on a base 32 to generate row address bits, and a multiplexer for changing a position of output bits of base-32 counter according to data rate selection signals, to variably generate the row address bits.
Claims20
An interleave read address generator comprising:
- a base-18 counter for counting a clock input to generate column address bits;
- and
- a base-32 counter being enabled in response to a carry output from said base-18 counter, for counting the clock input to generate row address bits.
An interleave read address generator comprising:
- a base-18 counter for counting a clock input to generate column address bits;
- and
- a base-32 counter being enabled in response to a carry output from said base-18 counter, for counting the clock input to generate a count value;
- and
- a multiplexer for changing a position of output bits of said base-32 counter according to first through fourth data rate selection signals, to variably generate row address bits.
An interleave read address generator comprising:
- a base-18 counter having a clock terminal for counting a clock input to generate column address bits;
- and
- a base-32 counter having an enable terminal connected to a carry output of said base-18 counter and a clock terminal for counting said clock input, said base-32 counter being enabled in response to said carry output from said base-18 counter to count the clock input to generate row address bits.
Dependencies are inferred from the claim text.