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AssigneeApple Computer, Inc.
InventorDavid V. James
Estimating the term…
In a mixed-protocol multiple-processor cache coherence computer system one processor may support read-only and read-write lists while another processor may support only read-write lists. Data copied to a cache is called a cache line while a copy of the same data remaining in memory is called a memory line. A memory line is stale when its associated cache line has been modified. The main memory of the system always points to the processor at the head of each list and includes indications of fresh and stale memory line states. The present invention deletes the head entry of a read-only cache-sharing list where the head entry supports read-only operations and the next-list entry supports only read-write operations. The head of the list informs the next-list entry that the next-list entry is about to become the head of the list. The main memory then repositions its head-pointer to the next-list entry and changes the memory state from fresh to stale. The head of the list then informs the next-list entry that the deletion is complete and the old head is thus deleted from the list.
In a multi-processor computer system, a mixed-coherence-protocol method for deleting a head entry from a read-only list, comprising the steps of:
In a multi-processor computer system, a computer-readable medium embodying instructions for causing a device to delete a head entry from a read-only list, comprising the steps of:
In a multi-processor computer system, an apparatus for deleting a head entry from a read-only list, comprising:
Dependencies are inferred from the claim text.